Fitting Multilinear Polynomials for Logic Gate Networks
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Abstract (arXiv)
We study learnable logic gate networks that stack layers of 2-input Boolean gates to build combinational circuits. Every 2-input gate has a unique multilinear polynomial with 4 coefficients, so the 16 Boolean gates form a codebook of prototypes in a 4-dimensional space, reducing training to a vector-quantization problem. The baseline method, Soft-Mix, learns a 16-dimensional softmax over gate identities, but the codebook has rank~4: 11 of 15 simplex directions carry nullspace gradient, and at uniform initialization the backward signal vanishes exactly. We prove that no affine product reparameterization fixes the resulting interaction-coefficient starvation under STE, and show that the covariance Jacobian of soft-VQ selection bypasses it by coupling the starved coefficient to the always-active constant channel. Working in the 4-dimensional polynomial space reduces each neuron from 16 to 4 parameters. On seven datasets, at least one 4-parameter method matches or exceeds Soft-Mix on every dataset; the CovJac advantage over STE grows monotonically with interaction demand across all seven datasets. At depth, Soft-Mix collapses (-37.3pp on CIFAR-10 at 12 layers) while CovJac holds (-0.5pp on CIFAR-10, stable on MNIST).
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References · 15
- 2017Neural Discrete Representation Learningcited by 4,650
- 2016Categorical Reparameterization with Gumbel-Softmaxcited by 2,708
- 2013Estimating or Propagating Gradients Through Stochastic Neurons for Conditional Computationcited by 2,031
- 2018DARTS: Differentiable Architecture Searchcited by 1,782
- 2016The Concrete Distribution: A Continuous Relaxation of Discrete Random Variablescited by 1,135
- 2017Soft-to-Hard Vector Quantization for End-to-End Learning Compressible Representationscited by 149
- 2020Analyzing Differentiable Fuzzy Logic Operatorscited by 100
- 2023Straightening Out the Straight-Through Estimator: Overcoming Optimization Challenges in Vector Quantized Networkscited by 80
- 2022Deep Differentiable Logic Gate Networkscited by 67
- 2024Convolutional Differentiable Logic Gate Networkscited by 37
- 2023PolyLUT: Learning Piecewise Polynomials for Ultra-Low Latency FPGA LUT-based Inferencecited by 30
- 2024Differentiable Weightless Neural Networkscited by 27
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