mlsanityData to 7 Oct 2026

MetaML-Pro: Cross-Stage Design Flow Automation for Efficient Deep Learning Acceleration

arXiv 2502.05850 ↗First posted 9 Feb 2025cs.AR cs.LGcited by 4

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Abstract (arXiv)

This paper presents a unified framework for codifying and automating optimization strategies to efficiently deploy deep neural networks (DNNs) on resource-constrained hardware, such as FPGAs, while maintaining high performance, accuracy, and resource efficiency. Deploying DNNs on such platforms involves addressing the significant challenge of balancing performance, resource usage (e.g., DSPs and LUTs), and inference accuracy, which often requires extensive manual effort and domain expertise. Our novel approach addresses two core key issues: (i)~encoding custom optimization strategies and (ii)~enabling cross-stage optimization search. In particular, our proposed framework seamlessly integrates programmatic DNN optimization techniques with high-level synthesis (HLS)-based metaprogramming, leveraging advanced design space exploration (DSE) strategies like Bayesian optimization to automate both top-down and bottom-up design flows. Hence, we reduce the need for manual intervention and domain expertise. In addition, the framework introduces customizable optimization, transformation, and control blocks to enhance DNN accelerator performance and resource efficiency. Experimental results demonstrate up to a 92% DSP and 89% LUT usage reduction for select networks, while preserving accuracy, along with a 15.6-fold reduction in optimization time compared to grid search. These results highlight the potential for automating the generation of resource-efficient DNN accelerator designs with minimum effort.

Key facts. Cited by 4 papers in the map (data through 7 Oct 2026). Builds on 29 of its 69 references that are in the map. First posted on arXiv 9 Feb 2025.

Builds on

29 of 69 references.

References · 29

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  11. 2020AutoDNNchip: An Automated DNN Chip Predictor and Builder for Both FPGAs and ASICscited by 26
  12. 2021IronMan: GNN-assisted Design Space Exploration in High-Level Synthesis via Reinforcement Learningcited by 26
17 more
  1. 2021ScaleHLS: A New Scalable High-Level Synthesis Framework on Multi-Level Intermediate Representationcited by 21
  2. 2018Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAscited by 18
  3. 2020DNNExplorer: A Framework for Modeling and Exploring a Novel Paradigm of FPGA-based DNN Acceleratorcited by 15
  4. 2021HAO: Hardware-aware neural Architecture Optimization for Efficient Inferencecited by 14
  5. 2019Deep Neural Network Approximation for Custom Hardware: Where We've Been, Where We're Goingcited by 13
  6. 2021Enabling Design Methodologies and Future Trends for Edge AI: Specialization and Co-designcited by 13
  7. 2021Accelerating Recurrent Neural Networks for Gravitational Wave Experimentscited by 12
  8. 2022LL-GNN: Low Latency Graph Neural Networks on FPGAs for High Energy Physicscited by 12
  9. 2024Ultrafast jet classification on FPGAs for the HL-LHCcited by 12
  10. 2019NAIS: Neural Architecture and Implementation Search and its Applications in Autonomous Drivingcited by 9
  11. 2024HGQ: High Granularity Quantization for Real-time Neural Networks on FPGAscited by 9
  12. 2019Unrolling Ternary Neural Networkscited by 7
  13. 2022CODEBench: A Neural Architecture and Hardware Accelerator Co-Design Frameworkcited by 5
  14. 2020Effective Algorithm-Accelerator Co-design for AI Solutions on Edge Devicescited by 4
  15. 2023MetaML: Automating Customizable Cross-Stage Design-Flow for Deep Learning Accelerationcited by 3
  16. 2021HALF: Holistic Auto Machine Learning for FPGAscited by 2
  17. 2021Algorithm and Hardware Co-design for Reconfigurable CNN Acceleratorcited by 2

Built on by

Cited by year (2026 to 7 Oct)

Citing papers per year: 2025: 2; 2026: 2.

4 papers.

  1. 2025da4ml: Distributed Arithmetic for Real-time Neural Networks on FPGAscited by 8
  2. 2025hls4ml: A Flexible, Open-Source Platform for Deep Learning Acceleration on Reconfigurable Hardwarecited by 8
  3. 2026HGQ-LUT: Fast LUT-Aware Training and Efficient Architectures for DNN Inferencecited by 1
  4. 2026FQTree: Fine-grained Quantization and Hardware Generation of Boosted Decision Treescited by 0