NVCell: Standard Cell Layout in Advanced Technology Nodes with Reinforcement Learning
Not on the map. Why?
Abstract (arXiv)
High quality standard cell layout automation in advanced technology nodes is still challenging in the industry today because of complex design rules. In this paper we introduce an automatic standard cell layout generator called NVCell that can generate layouts with equal or smaller area for over 90% of single row cells in an industry standard cell library on an advanced technology node. NVCell leverages reinforcement learning (RL) to fix design rule violations during routing and to generate efficient placements.
Key facts. Cited by 7 papers in the map (data through 7 Oct 2026). Builds on 8 of its 20 references that are in the map. First posted on arXiv 9 Jul 2021.
Builds on
8 of 20 references.
References · 8
- 2017Proximal Policy Optimization Algorithmscited by 14,441
- 2017Neural Message Passing for Quantum Chemistrycited by 3,460
- 2013Playing Atari with Deep Reinforcement Learningcited by 3,211
- 2016OpenAI Gymcited by 1,684
- 2020Chip Placement with Deep Reinforcement Learningcited by 83
- 2019A Deep Reinforcement Learning Approach for Global Routingcited by 20
- 2020Attention Routing: track-assignment detailed routing using attention-based reinforcement learningcited by 11
- 2020Circuit Routing Using Monte Carlo Tree Search and Deep Neural Networkscited by 6
Built on by
Citing papers per year: 2021: 1; 2022: 1; 2023: 0; 2024: 3; 2025: 1; 2026: 1.
7 papers.
- 2024DRC-Coder: Automated DRC Checker Code Generation Using LLM Autonomous Agentcited by 15
- 2024Large Language Model (LLM) for Standard Cell Layout Design Optimizationcited by 9
- 2021AIRCHITECT: Learning Custom Architecture Design and Mapping Spacecited by 4
- 2024MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuningcited by 4
- 2022An Adversarial Active Sampling-based Data Augmentation Framework for Manufacturable Chip Designcited by 1
- 2025Pieceformer: Similarity-Driven Knowledge Transfer via Scalable Graph Transformer in VLSIcited by 0
- 2026TOPCELL: Topology Optimization of Standard Cell via LLMscited by 0
- 2026TOPCELL: Topology Optimization of Standard Cell via LLMs15 Apr 2026
- 2025Pieceformer: Similarity-Driven Knowledge Transfer via Scalable Graph Transformer in VLSI18 Jun 2025
- 2024DRC-Coder: Automated DRC Checker Code Generation Using LLM Autonomous Agent28 Nov 2024
- 2024MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning25 Jul 2024
- 2024Large Language Model (LLM) for Standard Cell Layout Design Optimization24 May 2024
- 2022An Adversarial Active Sampling-based Data Augmentation Framework for Manufacturable Chip Design27 Oct 2022
- 2021AIRCHITECT: Learning Custom Architecture Design and Mapping Space16 Aug 2021