Heterogeneous Data-Centric Architectures for Modern Data-Intensive Applications: Case Studies in Machine Learning and Databases
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Abstract (arXiv)
Today's computing systems require moving data back-and-forth between computing resources (e.g., CPUs, GPUs, accelerators) and off-chip main memory so that computation can take place on the data. Unfortunately, this data movement is a major bottleneck for system performance and energy consumption. One promising execution paradigm that alleviates the data movement bottleneck in modern and emerging applications is processing-in-memory (PIM), where the cost of data movement to/from main memory is reduced by placing computation capabilities close to memory. Naively employing PIM to accelerate data-intensive workloads can lead to sub-optimal performance due to the many design constraints PIM substrates impose. Therefore, many recent works co-design specialized PIM accelerators and algorithms to improve performance and reduce the energy consumption of (i) applications from various application domains; and (ii) various computing environments, including cloud systems, mobile systems, and edge devices. We showcase the benefits of co-designing algorithms and hardware in a way that efficiently takes advantage of the PIM paradigm for two modern data-intensive applications: (1) machine learning inference models for edge devices and (2) hybrid transactional/analytical processing databases for cloud systems. We follow a two-step approach in our system design. In the first step, we extensively analyze the computation and memory access patterns of each application to gain insights into its hardware/software requirements and major sources of performance and energy bottlenecks in processor-centric systems. In the second step, we leverage the insights from the first step to co-design algorithms and hardware accelerators to enable high-performance and energy-efficient data-centric architectures for each application.
Key facts. Cited by 1 paper in the map (data through 7 Oct 2026). Builds on 46 of its 188 references that are in the map. First posted on arXiv 29 May 2022.
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46 of 188 references.
References · 46
- 2014Show and Tell: A Neural Image Caption Generatorcited by 877
- 2014Long-term Recurrent Convolutional Networks for Visual Recognition and Descriptioncited by 483
- 2018Streaming End-to-end Speech Recognition For Mobile Devicescited by 230
- 2014Long Short-Term Memory Based Recurrent Neural Network Architectures for Large Vocabulary Speech Recognitioncited by 111
- 2018Exploring Architectures, Data and Units For Streaming End-to-End Speech Recognition with RNN-Transducercited by 95
- 2019Improving RNN Transducer Modeling for End-to-End Speech Recognitioncited by 68
- 2019RecNMP: Accelerating Personalized Recommendation with Near-Memory Processingcited by 49
- 2019TensorDIMM: A Practical Near-Memory Processing Architecture for Embeddings and Tensor Operations in Deep Learningcited by 42
- 2021RecSSD: Near Data Processing for Solid State Drive Based Recommendation Inferencecited by 35
- 2020A Modern Primer on Processing in Memorycited by 30
- 2018Neural Cache: Bit-Serial In-Cache Acceleration of Deep Neural Networkscited by 29
- 2021Google Neural Network Models for Edge Devices: Analyzing and Mitigating Machine Learning Inference Bottleneckscited by 22
34 more
- 2019Processing Data Where It Makes Sense: Enabling In-Memory Computationcited by 21
- 2017GraphR: Accelerating Graph Processing Using ReRAMcited by 19
- 2021SISA: Set-Centric Instruction Set Architecture for Graph Mining on Processing-in-Memory Systemscited by 17
- 2021Benchmarking Memory-Centric Computing Systems: Analysis of Real Processing-in-Memory Hardwarecited by 12
- 2017GRIM-Filter: Fast Seed Location Filtering in DNA Read Mapping Using Processing-in-Memory Technologiescited by 11
- 2020NATSA: A Near-Data Processing Accelerator for Time Series Analysiscited by 10
- 2021DAMOV: A New Methodology and Benchmark Suite for Evaluating Data Movement Bottleneckscited by 10
- 2021FORMS: Fine-grained Polarized ReRAM-based In-situ Computation for Mixed-signal DNN Acceleratorcited by 10
- 2019TitAnt: Online Real-time Transaction Fraud Detection in Ant Financialcited by 9
- 2020GenASM: A High-Performance, Low-Power Approximate String Matching Acceleration Framework for Genome Sequence Analysiscited by 9
- 2021SynCron: Efficient Synchronization Support for Near-Data-Processing Architecturescited by 9
- 2021Benchmarking a New Paradigm: An Experimental Analysis of a Real Processing-in-Memory Architecturecited by 9
- 2020NERO: A Near High-Bandwidth Memory Stencil Accelerator for Weather Prediction Modelingcited by 8
- 2021FPGA-Based Near-Memory Acceleration of Modern Data-Intensive Applicationscited by 8
- 2021Mitigating Edge Machine Learning Inference Bottlenecks: An Empirical Study on Accelerating Google Edge Modelscited by 7
- 2021QUAC-TRNG: High-Throughput True Random Number Generation Using Quadruple Row Activation in Commodity DRAM Chipscited by 7
- 2016Buddy-RAM: Improving the Performance and Efficiency of Bulk Bitwise Operations Using DRAMcited by 6
- 2018D-RaNGe: Using Commodity DRAM Devices to Generate True Random Numbers with Low Latency and High Throughputcited by 6
- 2019In-DRAM Bulk Bitwise Execution Enginecited by 6
- 2020Accelerating Genome Analysis: A Primer on an Ongoing Journeycited by 6
- 2020NOM: Network-On-Memory for Inter-Bank Data Transfer in Highly-Banked Memoriescited by 5
- 2020FIGARO: Improving System Performance via Fine-Grained In-DRAM Data Relocation and Cachingcited by 5
- 2020Intelligent Architectures for Intelligent Computing Systemscited by 5
- 2021Polynesia: Enabling Effective Hybrid Transactional/Analytical Databases with Specialized Hardware/Software Co-Designcited by 5
- 2021Casper: Accelerating Stencil Computation using Near-cache Processingcited by 5
- 2022GenStore: A High-Performance and Energy-Efficient In-Storage Computing System for Genome Sequence Analysiscited by 5
- 2022SeGraM: A Universal Hardware Accelerator for Genomic Sequence-to-Graph and Sequence-to-Sequence Mappingcited by 4
- 2022DR-STRaNGe: End-to-End System Design for DRAM-based True Random Number Generatorscited by 3
- 2016The Processing Using Memory Paradigm:In-DRAM Bulk Copy, Initialization, Bitwise AND and ORcited by 2
- 2017Accelerating Analytical Processing in MVCC using Fine-Granular High-Frequency Virtual Snapshottingcited by 1
- 2019BioSEAL: In-Memory Biological Sequence Alignment Accelerator for Large-Scale Genomic Datacited by 1
- 2019WiSer: A Highly Available HTAP DBMS for IoT Applicationscited by 1
- 2020Computing-in-Memory for Performance and Energy Efficient Homomorphic Encryptioncited by 1
- 2020Intelligent Architectures for Intelligent Machinescited by 1
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