NERO: A Near High-Bandwidth Memory Stencil Accelerator for Weather Prediction Modeling
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Abstract (arXiv)
Ongoing climate change calls for fast and accurate weather and climate modeling. However, when solving large-scale weather prediction simulations, state-of-the-art CPU and GPU implementations suffer from limited performance and high energy consumption. These implementations are dominated by complex irregular memory access patterns and low arithmetic intensity that pose fundamental challenges to acceleration. To overcome these challenges, we propose and evaluate the use of near-memory acceleration using a reconfigurable fabric with high-bandwidth memory (HBM). We focus on compound stencils that are fundamental kernels in weather prediction models. By using high-level synthesis techniques, we develop NERO, an FPGA+HBM-based accelerator connected through IBM CAPI2 (Coherent Accelerator Processor Interface) to an IBM POWER9 host system. Our experimental results show that NERO outperforms a 16-core POWER9 system by 4.2x and 8.3x when running two different compound stencil kernels. NERO reduces the energy consumption by 22x and 29x for the same two kernels over the POWER9 system with an energy efficiency of 1.5 GFLOPS/Watt and 17.3 GFLOPS/Watt. We conclude that employing near-memory acceleration solutions for weather prediction modeling is promising as a means to achieve both high performance and high energy efficiency.
Key facts. Cited by 8 papers in the map (data through 7 Oct 2026). First posted on arXiv 17 Sep 2020.
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Citing papers per year: 2022: 5; 2023: 1; 2024: 1; 2025: 1.
8 papers.
- 2024PIM-Opt: Demystifying Distributed Optimization Algorithms on a Real-World Processing-In-Memory Systemcited by 5
- 2022Machine Learning Training on a Real Processing-in-Memory Systemcited by 4
- 2022Accelerating Neural Network Inference with Processing-in-DRAM: From the Edge to the Cloudcited by 4
- 2022An Experimental Evaluation of Machine Learning Training on a Real Processing-in-Memory Systemcited by 2
- 2025From Loop Nests to Silicon: Mapping AI Workloads onto AMD NPUs with MLIR-AIRcited by 2
- 2022Heterogeneous Data-Centric Architectures for Modern Data-Intensive Applications: Case Studies in Machine Learning and Databasescited by 1
- 2022LEAPER: Fast and Accurate FPGA-based System Performance Prediction via Transfer Learningcited by 1
- 2023TransPimLib: A Library for Efficient Transcendental Functions on Processing-in-Memory Systemscited by 1
- 2025From Loop Nests to Silicon: Mapping AI Workloads onto AMD NPUs with MLIR-AIR16 Oct 2025
- 2024PIM-Opt: Demystifying Distributed Optimization Algorithms on a Real-World Processing-In-Memory System10 Apr 2024
- 2023TransPimLib: A Library for Efficient Transcendental Functions on Processing-in-Memory Systems3 Apr 2023
- 2022Accelerating Neural Network Inference with Processing-in-DRAM: From the Edge to the Cloud19 Sep 2022
- 2022LEAPER: Fast and Accurate FPGA-based System Performance Prediction via Transfer Learning22 Aug 2022
- 2022An Experimental Evaluation of Machine Learning Training on a Real Processing-in-Memory System16 Jul 2022
- 2022Machine Learning Training on a Real Processing-in-Memory System13 Jun 2022
- 2022Heterogeneous Data-Centric Architectures for Modern Data-Intensive Applications: Case Studies in Machine Learning and Databases29 May 2022