PhD Thesis Summary: Methods for Reliability Assessment and Enhancement of Deep Neural Network Hardware Accelerators
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Abstract (arXiv)
This manuscript summarizes the work and showcases the impact of the doctoral thesis by introducing novel, cost-efficient methods for assessing and enhancing the reliability of DNN hardware accelerators. A comprehensive Systematic Literature Review (SLR) was conducted, categorizing existing reliability assessment techniques, identifying research gaps, and leading to the development of new analytical reliability assessment tools. Additionally, this work explores the interplay between reliability, quantization, and approximation, proposing methodologies that optimize the trade-offs between computational efficiency and fault tolerance. Furthermore, a real-time, zero-overhead reliability enhancement technique, AdAM, was developed, providing fault tolerance comparable to traditional redundancy methods while significantly reducing hardware costs. The impact of this research extends beyond academia, contributing to multiple funded projects, masters courses, industrial collaborations, and the development of new tools and methodologies for efficient and reliable DNN hardware accelerators.
Key facts. Cited by 1 paper in the map (data through 14 Oct 2026). Builds on 16 of its 40 references that are in the map. First posted on arXiv 17 Feb 2026.
Builds on
16 of 40 references.
References · 16
- 2022A Comprehensive Survey on Model Quantization for Deep Neural Networks in Image Classificationcited by 65
- 2021Robust Machine Learning Systems: Challenges, Current Trends, Perspectives, and the Road Aheadcited by 41
- 2023A Systematic Literature Review on Hardware Reliability Assessment Methods for Deep Neural Networkscited by 23
- 2019When Single Event Upset Meets Deep Neural Networks: Observations, Explorations, and Remediescited by 15
- 2023DeepAxe: A Framework for Exploration of Approximation and Reliability Trade-offs in DNN Acceleratorscited by 11
- 2024Exploration of Activation Fault Reliability in Quantized Systolic Array-Based DNN Acceleratorscited by 9
- 2023DeepVigor: Vulnerability Value Ranges and Factors for DNNs' Reliability Assessmentcited by 7
- 2023Enhancing Fault Resilience of QNNs by Selective Neuron Splittingcited by 6
- 2023APPRAISER: DNN Fault Resilience Analysis Employing Approximation Errorscited by 5
- 2023Special Session: Approximation and Fault Resiliency of DNN Acceleratorscited by 5
- 2024SAFFIRA: a Framework for Assessing the Reliability of Systolic-Array-Based DNN Acceleratorscited by 5
- 2020CNN2Gate: Toward Designing a General Framework for Implementation of Convolutional Neural Networks on FPGAcited by 3
4 more
- 2023scaleTRIM: Scalable TRuncation-Based Integer Approximate Multiplier with Linearization and Compensationcited by 3
- 2023Noise-Tolerance GPU-based Age Estimation Using ResNet-50cited by 3
- 2024AdAM: Adaptive Fault-Tolerant Approximate Multiplier for Edge DNN Acceleratorscited by 2
- 2023LRDB: LSTM Raw data DNA Base-caller based on long-short term models in an active learning environmentcited by 1
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Citing papers per year: 2026: 1.
1 paper.
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- 2023FAQ: Mitigating the Impact of Faults in the Weight Memory of DNN Accelerators through Fault-Aware Quantization
- 2026REQAP: Resilient Weight Packing and Quantization for Edge DNN Acceleration
- 2025MAx-DNN: Multi-Level Arithmetic Approximation for Energy-Efficient DNN Hardware Accelerators
- 2021DNN-Life: An Energy-Efficient Aging Mitigation Framework for Improving the Lifetime of On-Chip Weight Memories in Deep Neural Network Hardware Architectures
- 2023Cross-Layer Optimization for Fault-Tolerant Deep Learning
- 2022enpheeph: A Fault Injection Framework for Spiking and Compressed Deep Neural Networks
- 2021HAO: Hardware-aware neural Architecture Optimization for Efficient Inference
- 2022An Algorithm-Hardware Co-design Framework to Overcome Imperfections of Mixed-signal DNN Accelerators