mlsanityData to 14 Oct 2026

REQAP: Resilient Weight Packing and Quantization for Edge DNN Acceleration

arXiv 2609.17555 ↗First posted 20 Jul 2026cs.AR cs.AI cs.LGcited by 0

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Abstract (arXiv)

Efficient deployment of Deep Neural Networks (DNNs) on edge accelerators requires aggressive model compression while maintaining reliability in fault-prone hardware environments. This paper presents a reliability-aware quantized weight packing methodology for systolic-array-based DNN accelerators. A sensitivity-driven mixed-precision quantization framework assigns layer-wise bit-widths according to accuracy impact while enforcing symmetric precision between weights and activations. A deterministic register-level packing strategy consolidates multiple heterogeneous operand pairs into fixed-width register words, enabling SIMD-within-a-register (SWAR) style parallel execution that reduces both memory footprint and execution cycles. To improve resilience against hardware faults, selective bit-level protection replicates the most significant bits (MSBs) of critical layers into unused register space, achieving TMR-style protection with minimal overhead. A systolic-array simulation framework is developed to evaluate the proposed packing and fault-tolerance mechanisms under realistic execution conditions. Simulations in AlexNet, VGG-11, and ResNet-18 demonstrate up to 62% memory reduction and up to 56% reduction in Multiply-Accumulate (MAC) operations, while significantly improving accuracy resilience under fault injection compared to baseline and fully protected models.

Key facts. No citing papers in the map yet (data through 14 Oct 2026). Builds on 7 of its 15 references that are in the map. First posted on arXiv 20 Jul 2026.

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7 of 15 references.

References · 7

  1. 2017Quantization and Training of Neural Networks for Efficient Integer-Arithmetic-Only Inferencecited by 1,593
  2. 2018HAQ: Hardware-Aware Automated Quantization with Mixed Precisioncited by 443
  3. 2017Bit Fusion: Bit-Level Dynamically Composable Architecture for Accelerating Deep Neural Networkscited by 109
  4. 2023DeepAxe: A Framework for Exploration of Approximation and Reliability Trade-offs in DNN Acceleratorscited by 11
  5. 2024Exploration of Activation Fault Reliability in Quantized Systolic Array-Based DNN Acceleratorscited by 9
  6. 2024AdAM: Adaptive Fault-Tolerant Approximate Multiplier for Edge DNN Acceleratorscited by 2
  7. 2026Fusion: A Framework for Unified Sequential Token AdaptatIon in VisiOn TraNsformerscited by 2

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  1. 2023FAQ: Mitigating the Impact of Faults in the Weight Memory of DNN Accelerators through Fault-Aware Quantization
  2. 2026PhD Thesis Summary: Methods for Reliability Assessment and Enhancement of Deep Neural Network Hardware Accelerators
  3. 2023Block-Wise Mixed-Precision Quantization: Enabling High Efficiency for Practical ReRAM-based DNN Accelerators
  4. 2024Exploring Quantization and Mapping Synergy in Hardware-Aware Deep Neural Network Accelerators
  5. 2023Hardware-Aware DNN Compression via Diverse Pruning and Mixed-Precision Quantization
  6. 2026Bitwise Systolic Array Architecture for Runtime-Reconfigurable Multi-precision Quantized Multiplication on Hardware Accelerators
  7. 2025A Flexible Precision Scaling Deep Neural Network Accelerator with Efficient Weight Combination
  8. 2023On-Chip Hardware-Aware Quantization for Mixed Precision Neural Networks