SAFFIRA: a Framework for Assessing the Reliability of Systolic-Array-Based DNN Accelerators
Not on the map. Why?
Abstract (arXiv)
Systolic array has emerged as a prominent architecture for Deep Neural Network (DNN) hardware accelerators, providing high-throughput and low-latency performance essential for deploying DNNs across diverse applications. However, when used in safety-critical applications, reliability assessment is mandatory to guarantee the correct behavior of DNN accelerators. While fault injection stands out as a well-established practical and robust method for reliability assessment, it is still a very time-consuming process. This paper addresses the time efficiency issue by introducing a novel hierarchical software-based hardware-aware fault injection strategy tailored for systolic array-based DNN accelerators.
Key facts. Cited by 5 papers in the map (data through 14 Oct 2026). Builds on 7 of its 32 references that are in the map. First posted on arXiv 5 Mar 2024.
Builds on
7 of 32 references.
References · 7
- 2023A Systematic Literature Review on Hardware Reliability Assessment Methods for Deep Neural Networkscited by 23
- 2023DeepAxe: A Framework for Exploration of Approximation and Reliability Trade-offs in DNN Acceleratorscited by 11
- 2024Exploration of Activation Fault Reliability in Quantized Systolic Array-Based DNN Acceleratorscited by 9
- 2023APPRAISER: DNN Fault Resilience Analysis Employing Approximation Errorscited by 5
- 2023Special Session: Approximation and Fault Resiliency of DNN Acceleratorscited by 5
- 2015Caffe con Troll: Shallow Ideas to Speed Up Deep Learningcited by 4
- 2019iFDK: A Scalable Framework for Instant High-resolution Image Reconstructioncited by 3
Built on by
Citing papers per year: 2024: 1; 2025: 1; 2026: 3.
5 papers.
- 2024DeepVigor+: Scalable and Accurate Semi-Analytical Fault Resilience Analysis for Deep Neural Networkcited by 1
- 2025FORTALESA: Fault-Tolerant Reconfigurable Systolic Array for DNN Inferencecited by 1
- 2026PhD Thesis Summary: Methods for Reliability Assessment and Enhancement of Deep Neural Network Hardware Acceleratorscited by 1
- 2026FLARE: One-Shot PE-Level Fault Localization in Systolic Arrays via Algebraic Test Vectorscited by 1
- 2026BLADE: ReliaBle Dynamic Hardware-Aware SNN-ANN Boundary SeLection for Event-BAseD Object DEtectioncited by 0
- 2026BLADE: ReliaBle Dynamic Hardware-Aware SNN-ANN Boundary SeLection for Event-BAseD Object DEtection22 Jul 2026
- 2026FLARE: One-Shot PE-Level Fault Localization in Systolic Arrays via Algebraic Test Vectors9 May 2026
- 2026PhD Thesis Summary: Methods for Reliability Assessment and Enhancement of Deep Neural Network Hardware Accelerators17 Feb 2026
- 2025FORTALESA: Fault-Tolerant Reconfigurable Systolic Array for DNN Inference6 Mar 2025
- 2024DeepVigor+: Scalable and Accurate Semi-Analytical Fault Resilience Analysis for Deep Neural Network21 Oct 2024