Inter-patient ECG Arrhythmia Classification with LGNs and LUTNs
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Abstract (arXiv)
Deep Differentiable Logic Gate Networks (LGNs) and Lookup Table Networks (LUTNs) are demonstrated to be suitable for the automatic classification of electrocardiograms (ECGs) using the inter-patient paradigm. The methods are benchmarked using the MIT-BIH arrhythmia data set, achieving up to 94.28% accuracy and a jkappa index of 0.683 on a four-class classification problem. Our models use between 2.89k and 6.17k FLOPs, including preprocessing and readout, which is three to six orders of magnitude less compared to SOTA methods. A novel preprocessing method is utilized that attains superior performance compared to existing methods for both the mixed-patient and inter-patient paradigms. In addition, a novel method for training the Lookup Tables (LUTs) in LUTNs is devised that uses the Boolean equation of a multiplexer (MUX). Additionally, rate coding was utilized for the first time in these LGNs and LUTNs, enhancing the performance of LGNs. Furthermore, it is the first time that LGNs and LUTNs have been benchmarked on the MIT-BIH arrhythmia dataset using the inter-patient paradigm. Using an Artix 7 FPGA, between 2000 and 2990 LUTs were needed, and between 5 to 7 mW (i.e. 50 pJ to 70 pJ per inference) was estimated for running these models. The performance in terms of both accuracy and jkappa-index is significantly higher compared to previous LGN results. These positive results suggest that one can utilize LGNs and LUTNs for the detection of arrhythmias at extremely low power and high speeds in heart implants or wearable devices, even for patients not included in the training set.
Key facts. Cited by 1 paper in the map (data through 14 Oct 2026). Builds on 13 of its 34 references that are in the map. First posted on arXiv 16 Jan 2026.
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13 of 34 references.
References · 13
- 2016XNOR-Net: ImageNet Classification Using Binary Convolutional Neural Networkscited by 849
- 2022Deep Differentiable Logic Gate Networkscited by 67
- 2020LogicNets: Co-Designed Neural Networks and Circuits for Extreme-Throughput Applicationscited by 57
- 2024Convolutional Differentiable Logic Gate Networkscited by 37
- 2021Ps and Qs: Quantization-aware pruning for efficient low latency neural network inferencecited by 31
- 2023PolyLUT: Learning Piecewise Polynomials for Ultra-Low Latency FPGA LUT-based Inferencecited by 30
- 2019LUTNet: Rethinking Inference in FPGA Soft Logiccited by 28
- 2024Differentiable Weightless Neural Networkscited by 28
- 2019LUTNet: Learning FPGA Configurations for Highly Efficient Neural Network Inferencecited by 23
- 2024NeuraLUT: Hiding Neural Network Density in Boolean Synthesizable Functionscited by 21
- 2025Recurrent Deep Differentiable Logic Gate Networkscited by 12
- 2025WARP-LUTs -- Walsh-Assisted Relaxation for Probabilistic Look Up Tablescited by 6
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