mlsanityData to 14 Oct 2026

MetaML: Automating Customizable Cross-Stage Design-Flow for Deep Learning Acceleration

arXiv 2306.08746 ↗First posted 14 Jun 2023cs.LG cs.ARcited by 3

Not on the map. Why?

Abstract (arXiv)

This paper introduces a novel optimization framework for deep neural network (DNN) hardware accelerators, enabling the rapid development of customized and automated design flows. More specifically, our approach aims to automate the selection and configuration of low-level optimization techniques, encompassing DNN and FPGA low-level optimizations. We introduce novel optimization and transformation tasks for building design-flow architectures, which are highly customizable and flexible, thereby enhancing the performance and efficiency of DNN accelerators. Our results demonstrate considerable reductions of up to 92% in DSP usage and 89% in LUT usage for two networks, while maintaining accuracy and eliminating the need for human effort or domain expertise. In comparison to state-of-the-art approaches, our design achieves higher accuracy and utilizes three times fewer DSP resources, underscoring the advantages of our proposed framework.

Key facts. Cited by 3 papers in the map (data through 14 Oct 2026). Builds on 18 of its 37 references that are in the map. First posted on arXiv 14 Jun 2023.

Builds on

18 of 37 references.

References · 18

  1. 2015Deep Residual Learning for Image Recognitioncited by 52,096
  2. 2014Very Deep Convolutional Networks for Large-Scale Image Recognitioncited by 15,364
  3. 2017Efficient Processing of Deep Neural Networks: A Tutorial and Surveycited by 434
  4. 2016FINN: A Framework for Fast, Scalable Binarized Neural Network Inferencecited by 150
  5. 2018Fast inference of deep neural networks in FPGAs for particle physicscited by 133
  6. 2020Automatic heterogeneous quantization of deep neural networks for low-latency inference on the edge for particle detectorscited by 80
  7. 2020LogicNets: Co-Designed Neural Networks and Circuits for Extreme-Throughput Applicationscited by 57
  8. 2019Hardware/Software Co-Exploration of Neural Architecturescited by 50
  9. 2019FPGA/DNN Co-Design: An Efficient Design Methodology for IoT Intelligence on the Edgecited by 48
  10. 2020Best of Both Worlds: AutoML Codesign of a CNN and its Hardware Acceleratorcited by 30
  11. 2020AutoDNNchip: An Automated DNN Chip Predictor and Builder for Both FPGAs and ASICscited by 26
  12. 2018Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAscited by 18
6 more
  1. 2020DNNExplorer: A Framework for Modeling and Exploring a Novel Paradigm of FPGA-based DNN Acceleratorcited by 18
  2. 2021HAO: Hardware-aware neural Architecture Optimization for Efficient Inferencecited by 16
  3. 2021Accelerating Recurrent Neural Networks for Gravitational Wave Experimentscited by 12
  4. 2020Effective Algorithm-Accelerator Co-design for AI Solutions on Edge Devicescited by 4
  5. 2021HALF: Holistic Auto Machine Learning for FPGAscited by 2
  6. 2021Algorithm and Hardware Co-design for Reconfigurable CNN Acceleratorcited by 2

Built on by

Cited by year

Citing papers per year: 2024: 1; 2025: 2.

3 papers.

  1. 2024HGQ: High Granularity Quantization for Real-time Neural Networks on FPGAscited by 9
  2. 2025hls4ml: A Flexible, Open-Source Platform for Deep Learning Acceleration on Reconfigurable Hardwarecited by 9
  3. 2025MetaML-Pro: Cross-Stage Design Flow Automation for Efficient Deep Learning Accelerationcited by 4