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Assessing Economic Viability: A Comparative Analysis of Total Cost of Ownership for Domain-Adapted Large Language Models versus State-of-the-art Counterparts in Chip Design Coding Assistance

arXiv 2404.08850 ↗First posted 12 Apr 2024cs.AI cs.CE cs.LGcited by 0

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Abstract (arXiv)

This paper presents a comparative analysis of total cost of ownership (TCO) and performance between domain-adapted large language models (LLM) and state-of-the-art (SoTA) LLMs , with a particular emphasis on tasks related to coding assistance for chip design. We examine the TCO and performance metrics of a domain-adaptive LLM, ChipNeMo, against two leading LLMs, Claude 3 Opus and ChatGPT-4 Turbo, to assess their efficacy in chip design coding generation. Through a detailed evaluation of the accuracy of the model, training methodologies, and operational expenditures, this study aims to provide stakeholders with critical information to select the most economically viable and performance-efficient solutions for their specific needs. Our results underscore the benefits of employing domain-adapted models, such as ChipNeMo, that demonstrate improved performance at significantly reduced costs compared to their general-purpose counterparts. In particular, we reveal the potential of domain-adapted LLMs to decrease TCO by approximately 90%-95%, with the cost advantages becoming increasingly evident as the deployment scale expands. With expansion of deployment, the cost benefits of ChipNeMo become more pronounced, making domain-adaptive LLMs an attractive option for organizations with substantial coding needs supported by LLMs

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References · 9

  1. 2022CodeGen: An Open Large Language Model for Code with Multi-Turn Program Synthesiscited by 885
  2. 2023VerilogEval: Evaluating Large Language Models for Verilog Code Generationcited by 252
  3. 2023ChipNeMo: Domain-Adapted LLMs for Chip Designcited by 174
  4. 2023Chip-Chat: Challenges and Opportunities in Conversational Hardware Designcited by 140
  5. 2023ChatEDA: A Large Language Model Powered Autonomous Agent for EDAcited by 122
  6. 2022Benchmarking Large Language Models for Automated Verilog RTL Code Generationcited by 115
  7. 2023ChipGPT: How far are we from natural language hardware designcited by 105
  8. 2024Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation frameworkcited by 36
  9. 2024Hardware Phi-1.5B: A Large Language Model Encodes Hardware Domain Specific Knowledgecited by 10

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