SMOF: Streaming Modern CNNs on FPGAs with Smart Off-Chip Eviction
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Abstract (arXiv)
Convolutional Neural Networks (CNNs) have demonstrated their effectiveness in numerous vision tasks. However, their high processing requirements necessitate efficient hardware acceleration to meet the application's performance targets. In the space of FPGAs, streaming-based dataflow architectures are often adopted by users, as significant performance gains can be achieved through layer-wise pipelining and reduced off-chip memory access by retaining data on-chip. However, modern topologies, such as the UNet, YOLO, and X3D models, utilise long skip connections, requiring significant on-chip storage and thus limiting the performance achieved by such system architectures. The paper addresses the above limitation by introducing weight and activation eviction mechanisms to off-chip memory along the computational pipeline, taking into account the available compute and memory resources. The proposed mechanism is incorporated into an existing toolflow, expanding the design space by utilising off-chip memory as a buffer. This enables the mapping of such modern CNNs to devices with limited on-chip memory, under the streaming architecture design approach. SMOF has demonstrated the capacity to deliver competitive and, in some cases, state-of-the-art performance across a spectrum of computer vision tasks, achieving up to 10.65 X throughput improvement compared to previous works.
Key facts. No citing papers in the map yet (data through 7 Oct 2026). Builds on 19 of its 45 references that are in the map. First posted on arXiv 27 Mar 2024.
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19 of 45 references.
References · 19
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7 more
- 2023HARFLOW3D: A Latency-Oriented 3D-CNN Accelerator Toolflow for HAR on FPGA Devicescited by 5
- 2023SATAY: A Streaming Architecture Toolflow for Accelerating YOLO Models on FPGA Devicescited by 4
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- 2023AutoWS: Automate Weights Streaming in Layer-wise Pipelined DNN Acceleratorscited by 2
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