HARFLOW3D: A Latency-Oriented 3D-CNN Accelerator Toolflow for HAR on FPGA Devices
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Abstract (arXiv)
For Human Action Recognition tasks (HAR), 3D Convolutional Neural Networks have proven to be highly effective, achieving state-of-the-art results. This study introduces a novel streaming architecture based toolflow for mapping such models onto FPGAs considering the model's inherent characteristics and the features of the targeted FPGA device. The HARFLOW3D toolflow takes as input a 3D CNN in ONNX format and a description of the FPGA characteristics, generating a design that minimizes the latency of the computation. The toolflow is comprised of a number of parts, including i) a 3D CNN parser, ii) a performance and resource model, iii) a scheduling algorithm for executing 3D models on the generated hardware, iv) a resource-aware optimization engine tailored for 3D models, v) an automated mapping to synthesizable code for FPGAs. The ability of the toolflow to support a broad range of models and devices is shown through a number of experiments on various 3D CNN and FPGA system pairs. Furthermore, the toolflow has produced high-performing results for 3D CNN models that have not been mapped to FPGAs before, demonstrating the potential of FPGA-based systems in this space. Overall, HARFLOW3D has demonstrated its ability to deliver competitive latency compared to a range of state-of-the-art hand-tuned approaches being able to achieve up to 5× better performance compared to some of the existing works.
Key facts. Cited by 5 papers in the map (data through 7 Oct 2026). Builds on 6 of its 21 references that are in the map. First posted on arXiv 30 Mar 2023.
Builds on
6 of 21 references.
References · 6
- 2018SlowFast Networks for Video Recognitioncited by 1,862
- 2017A Closer Look at Spatiotemporal Convolutions for Action Recognitioncited by 1,139
- 2020X3D: Expanding Architectures for Efficient Video Recognitioncited by 635
- 2017Can Spatiotemporal 3D CNNs Retrace the History of 2D CNNs and ImageNet?cited by 551
- 2016FINN: A Framework for Fast, Scalable Binarized Neural Network Inferencecited by 141
- 2018Toolflows for Mapping Convolutional Neural Networks on FPGAs: A Survey and Future Directionscited by 27
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Citing papers per year: 2023: 3; 2024: 1; 2025: 1.
5 papers.
- 2023SATAY: A Streaming Architecture Toolflow for Accelerating YOLO Models on FPGA Devicescited by 4
- 2023FMM-X3D: FPGA-based modeling and mapping of X3D for Human Action Recognitioncited by 2
- 2023fpgaHART: A toolflow for throughput-oriented acceleration of 3D CNNs for HAR onto FPGAscited by 2
- 2025FPGA-based Acceleration for Convolutional Neural Networks: A Comprehensive Reviewcited by 1
- 2024SMOF: Streaming Modern CNNs on FPGAs with Smart Off-Chip Evictioncited by 0
- 2025FPGA-based Acceleration for Convolutional Neural Networks: A Comprehensive Review4 May 2025
- 2024SMOF: Streaming Modern CNNs on FPGAs with Smart Off-Chip Eviction27 Mar 2024
- 2023SATAY: A Streaming Architecture Toolflow for Accelerating YOLO Models on FPGA Devices4 Sep 2023
- 2023fpgaHART: A toolflow for throughput-oriented acceleration of 3D CNNs for HAR onto FPGAs31 May 2023
- 2023FMM-X3D: FPGA-based modeling and mapping of X3D for Human Action Recognition29 May 2023