Computing-In-Memory Aware Model Adaption For Edge Devices
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Abstract (arXiv)
Computing-in-Memory (CIM) macros have gained popularity for deep learning acceleration due to their highly parallel computation and low power consumption. However, limited macro size and ADC precision introduce throughput and accuracy bottlenecks. This paper proposes a two-stage CIM-aware model adaptation process. The first stage compresses the model and reallocates resources based on layer importance and macro size constraints, reducing model weight loading latency while improving resource utilization and maintaining accuracy. The second stage performs quantization-aware training, incorporating partial sum quantization and ADC precision to mitigate quantization errors in inference. The proposed approach enhances CIM array utilization to 90%, enables concurrent activation of up to 256 word lines, and achieves up to 93% compression, all while preserving accuracy comparable to previous methods.
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- 2026NANQ: Noise-Floor-Aware Mixed-Precision Non-Uniform Quantization for Analog Compute-in-Memory
- 2025Column-wise Quantization of Weights and Partial Sums for Accurate and Efficient Compute-In-Memory Accelerators
- 2026Mixed-Precision Training and Compilation for RRAM-based Computing-in-Memory Accelerators
- 2025A Hybrid-Domain Floating-Point Compute-in-Memory Architecture for Efficient Acceleration of High-Precision Deep Neural Networks ↗
- 2025Extending Straight-Through Estimation for Robust Neural Networks on Analog CIM Hardware
- 2025QS4D: Quantization-aware training for efficient hardware deployment of structured state-space sequential models
- 2026QMC: Efficient SLM Edge Inference via Outlier-Aware Quantization and Emergent Memories Co-Design
- 2024DNN Memory Footprint Reduction via Post-Training Intra-Layer Multi-Precision Quantization