MAVIREC: ML-Aided Vectored IR-DropEstimation and Classification
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Abstract (arXiv)
Vectored IR drop analysis is a critical step in chip signoff that checks the power integrity of an on-chip power delivery network. Due to the prohibitive runtimes of dynamic IR drop analysis, the large number of test patterns must be whittled down to a small subset of worst-case IR vectors. Unlike the traditional slow heuristic method that select a few vectors with incomplete coverage, MAVIREC uses machine learning techniques -- 3D convolutions and regression-like layers -- for accurately recommending a larger subset of test patterns that exercise worst-case scenarios. In under 30 minutes, MAVIREC profiles 100K-cycle vectors and provides better coverage than a state-of-the-art industrial flow. Further, MAVIREC's IR drop predictor shows 10x speedup with under 4mV RMSE relative to an industrial flow.
Key facts. Cited by 10 papers in the map (data through 7 Oct 2026). First posted on arXiv 19 Dec 2020.
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Citing papers per year: 2021: 1; 2022: 1; 2023: 0; 2024: 3; 2025: 3; 2026: 2.
10 papers.
- 2022CircuitNet: An Open-Source Dataset for Machine Learning Applications in Electronic Design Automation (EDA)cited by 10
- 2024HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyondcited by 8
- 2024PDNNet: PDN-Aware GNN-CNN Heterogeneous Network for Dynamic IR Drop Predictioncited by 3
- 2025CFIRSTNET: Comprehensive Features for Static IR Drop Estimation with Neural Networkcited by 1
- 2026GIF: A Conditional Multimodal Generative Framework for IR Drop Imaging in Chip Layoutscited by 1
- 2021Encoder-Decoder Networks for Analyzing Thermal and Power Delivery Networkscited by 0
- 2024On Robustness and Generalization of ML-Based Congestion Predictors to Valid and Imperceptible Perturbationscited by 0
- 2025Estimating Voltage Drop: Models, Features and Data Representation Towards a Neural Surrogatecited by 0
- 2025DALI-PD: Diffusion-based Synthetic Layout Heatmap Generation for ML in Physical Designcited by 0
- 2026Graph Computation Meets Circuit Algebra: A Task-Aligned Analysis of Graph Neural Networks for Electronic Design Automationcited by 0
- 2026Graph Computation Meets Circuit Algebra: A Task-Aligned Analysis of Graph Neural Networks for Electronic Design Automation8 May 2026
- 2026GIF: A Conditional Multimodal Generative Framework for IR Drop Imaging in Chip Layouts11 Apr 2026
- 2025DALI-PD: Diffusion-based Synthetic Layout Heatmap Generation for ML in Physical Design13 Jul 2025
- 2025CFIRSTNET: Comprehensive Features for Static IR Drop Estimation with Neural Network13 Feb 2025
- 2025Estimating Voltage Drop: Models, Features and Data Representation Towards a Neural Surrogate7 Feb 2025
- 2024HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond1 May 2024
- 2024PDNNet: PDN-Aware GNN-CNN Heterogeneous Network for Dynamic IR Drop Prediction27 Mar 2024
- 2024On Robustness and Generalization of ML-Based Congestion Predictors to Valid and Imperceptible Perturbations29 Feb 2024
- 2022CircuitNet: An Open-Source Dataset for Machine Learning Applications in Electronic Design Automation (EDA)1 Aug 2022
- 2021Encoder-Decoder Networks for Analyzing Thermal and Power Delivery Networks27 Oct 2021