An Executable Benchmark for LLM-Based HLS Repair:Design Complexity and Repair Underconstraint
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Abstract (arXiv)
Automated repair of High-Level Synthesis (HLS) designs using large language models (LLMs) is an emerging but underexplored problem. While LLM-based repair shows strong results on register-transfer level (RTL) Verilog, the only prior systematic study of HLS logic repair reports just 10.5% correction accuracy for GPT-4, with no analysis of why repair fails or what drives difficulty. We present the first comprehensive evaluation of LLM-based HLS repair across four models (GPT-4o, GPT-4o-mini, GPT-5.4, and Claude Opus 4.6) on 125 benchmark instances spanning eight logic bug types across three open-source HLS suites (CHStone, MachSuite, Polybench). We construct the first executable APR-style HLS repair benchmark with suite-specific functional oracles, enabling pass@k evaluation rather than the string-match approximations used in prior work. Design context and scale, rather than bug type alone, dominate repair difficulty: repair rates range from 6-45% on complex cryptographic kernels (CHStone) to 81-93% on compact algorithmic kernels (MachSuite) despite identical bug type distributions. We introduce solution multiplicity, the fraction of distinct patches generated across repeated repair attempts, as an empirical measure of repair underconstraint, and show it strongly predicts repair failure across all four models (Spearman rho = -0.393, p = 6.61 x 10^-20). Frontier models reduce underconstrained instances from 41-46 (GPT-4o, GPT-4o-mini) to just 3 (Claude Opus 4.6), with pass@1 improving from 42-53% to 73-76%. SHFT bugs remain consistently hard across all models, and semantic bug classes such as buffer indexing become reliably repairable only at frontier scale. These findings show that future APR benchmarks must include complex, executable, and weakly identifiable designs that remain challenging after frontier LLM repair.
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References · 13
- 2021Evaluating Large Language Models Trained on Codecited by 8,320
- 2023RTLFixer: Automatically Fixing RTL Syntax Errors with Large Language Modelscited by 100
- 2024CraftRTL: High-quality Synthetic Data Generation for Verilog Code Models with Correct-by-Construction Non-Textual Representations and Targeted Code Repaircited by 42
- 2024HDLdebugger: Streamlining HDL debugging with Large Language Modelscited by 26
- 2024HLSPilot: LLM-based High-Level Synthesiscited by 25
- 2024Location is Key: Leveraging Large Language Model for Functional Bug Localization in Verilogcited by 10
- 2026HWE-Bench: Benchmarking LLM Agents on Real-World Hardware Bug Repair Taskscited by 8
- 2024SynthAI: A Multi Agent Generative AI Framework for Automated Modular HLS Design Generationcited by 6
- 2025HLSDebugger: Identification and Correction of Logic Bugs in HLS Code with LLM Solutionscited by 5
- 2026Rethinking Code Complexity Through the Lens of Large Language Modelscited by 4
- 2025VeriRAG: A Retrieval-Augmented Framework for Automated RTL Testability Repaircited by 3
- 2025ARSP: Automated Repair of Verilog Designs via Semantic Partitioningcited by 2
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