mlsanityData to 14 Oct 2026

RISC-V and machine learning: a survey

arXiv 2609.20677 ↗First posted 17 Sep 2026cs.LG cs.ARcited by 0

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Abstract (arXiv)

The intersection of open-source processor architectures and machine learning is driving the demand for customizable, efficient, and accessible hardware. This survey examines the state of the RISC-V ISA in machine learning applications, analyzing current capabilities, challenges, and future directions based on recent research. The analysis covers academic and commercial implementations, software frameworks, and real-world applications. The RISC-V machine learning ecosystem is evaluated, from instruction set extensions and core implementations to compiler optimizations and deployment strategies. Key contributions include a unified taxonomy of RISC-V ML implementations, a comparative analysis of performance and design trade-offs, an evaluation of software toolchain maturity, and the identification of emerging trends in instruction set extensions and specialized accelerators. Findings reveal progress in energy efficiency, specialized instruction development, and framework integration, while highlighting challenges in standardization, verification complexity, and ecosystem fragmentation. The analysis proposes four research directions to address current limitations: specialized neural processing extensions, adaptive and modular processor architectures, security frameworks, and energy-efficient multi-domain architectures. These directions provide a roadmap for advancing RISC-V as a foundational platform for next-generation machine learning systems.

Key facts. No citing papers in the map yet (data through 14 Oct 2026). Builds on 27 of its 134 references that are in the map. First posted on arXiv 17 Sep 2026.

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27 of 134 references.

References · 27

  1. 2016FINN: A Framework for Fast, Scalable Binarized Neural Network Inferencecited by 150
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  3. 2018Glow: Graph Lowering Compiler Techniques for Neural Networkscited by 75
  4. 2022TinyIREE: An ML Execution Environment for Embedded Systems from Compilation to Deploymentcited by 12
  5. 2022Composable and Modular Code Generation in MLIR: A Structured and Retargetable Approach to Tensor Compiler Constructioncited by 8
  6. 2022Compiler Support for Sparse Tensor Computations in MLIRcited by 8
  7. 2024GAP9Shield: A 150GOPS AI-capable Ultra-low Power Module for Vision and Ranging Applications on Nano-dronescited by 8
  8. 2020XpulpNN: Enabling Energy Efficient and Flexible Inference of Quantized Neural Network on RISC-V based IoT End Nodescited by 7
  9. 2023DARKSIDE: A Heterogeneous RISC-V Compute Cluster for Extreme-Edge On-Chip DNN Inference and Trainingcited by 6
  10. 2024Locking Machine Learning Models into Hardwarecited by 6
  11. 2024Mixed-precision Neural Networks on RISC-V Cores: ISA extensions for Multi-Pumped Soft SIMD Operationscited by 5
  12. 2020LiteX: an open-source SoC builder and library based on Migen Python DSLcited by 4
15 more
  1. 2024xTern: Energy-Efficient Ternary Neural Network Inference on RISC-V-Based Edge Systemscited by 4
  2. 2025VEXP: A Low-Cost RISC-V ISA Extension for Accelerated Softmax Computation in Transformerscited by 4
  3. 2024Towards a high-performance AI compiler with upstream MLIRcited by 3
  4. 2025Hardware/Software Co-Design of RISC-V Extensions for Accelerating Sparse DNNs on FPGAscited by 3
  5. 2021A Survey on RISC-V Security: Hardware and Architecturecited by 2
  6. 2022HULK-V: a Heterogeneous Ultra-low-power Linux capable RISC-V SoCcited by 2
  7. 2025Lightweight Software Kernels and Hardware Extensions for Efficient Sparse Deep Neural Networks on Microcontrollerscited by 2
  8. 2025Support Vector Machines Classification on Bendable RISC-Vcited by 2
  9. 2023A Chisel Framework for Flexible Design Space Exploration through a Functional Approachcited by 1
  10. 2023VEDLIoT -- Next generation accelerated AIoT systems and applicationscited by 1
  11. 2023Challenges and Opportunities in the Co-design of Convolutions and RISC-V Vector Processorscited by 1
  12. 2024PCG: Mitigating Conflict-based Cache Side-channel Attacks with Prefetchingcited by 1
  13. 2025On-Device Federated Continual Learning on RISC-V-based Ultra-Low-Power SoC for Intelligent Nano-Drone Swarmscited by 1
  14. 2025Towards Zero-Stall Matrix Multiplication on Energy-Efficient RISC-V Clusters for Machine Learning Accelerationcited by 1
  15. 2025MARVEL: An End-to-End Framework for Generating Model-Class Aware Custom RISC-V Extensions for Lightweight AIcited by 1

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