TinyIREE: An ML Execution Environment for Embedded Systems from Compilation to Deployment
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Abstract (arXiv)
Machine learning model deployment for training and execution has been an important topic for industry and academic research in the last decade. Much of the attention has been focused on developing specific toolchains to support acceleration hardware. In this paper, we present IREE, a unified compiler and runtime stack with the explicit goal to scale down machine learning programs to the smallest footprints for mobile and edge devices, while maintaining the ability to scale up to larger deployment targets. IREE adopts a compiler-based approach and optimizes for heterogeneous hardware accelerators through the use of the MLIR compiler infrastructure which provides the means to quickly design and implement multi-level compiler intermediate representations (IR). More specifically, this paper is focused on TinyIREE, which is a set of deployment options in IREE that accommodate the limited memory and computation resources in embedded systems and bare-metal platforms, while also demonstrating IREE's intuitive workflow that generates workloads for different ISA extensions and ABIs through LLVM.
Key facts. Cited by 12 papers in the map (data through 7 Oct 2026). First posted on arXiv 28 May 2022.
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Citing papers per year: 2022: 1; 2023: 0; 2024: 2; 2025: 4; 2026: 5.
12 papers.
- 2026Embodied Foundation Models at the Edge: A Survey of Deployment Constraints and Mitigation Strategiescited by 6
- 2024MATCH: Model-Aware TVM-based Compilation for Heterogeneous Edge Devicescited by 5
- 2026Fuzzy PyTorch: Rapid Numerical Variability Evaluation for Deep Learning Modelscited by 2
- 2022Productive Reproducible Workflows for DNNs: A Case Study for Industrial Defect Detectioncited by 1
- 2025Ariel-ML: Computing Parallelization with Embedded Rust for Neural Networks on Heterogeneous Multi-core Microcontrollerscited by 1
- 2024Full-stack evaluation of Machine Learning inference workloads for RISC-V systemscited by 0
- 2025Fake Runs, Real Fixes -- Analyzing xPU Performance Through Simulationcited by 0
- 2025A High-Level Compiler Integration Approach for Deep Learning Accelerators Supporting Abstraction and Optimizationcited by 0
- 2025XTC, A Research Platform for Optimizing AI Workload Operatorscited by 0
- 2026Optimizing Tensor Train Decomposition in DNNs for RISC-V Architectures Using Design Space Exploration and Compiler Optimizationscited by 0
- 2026Meganeura: Portable GPU Training and Inference through Vulkan and Metalcited by 0
- 2026RISC-V and machine learning: a surveycited by 0
- 2026RISC-V and machine learning: a survey17 Sep 2026
- 2026Meganeura: Portable GPU Training and Inference through Vulkan and Metal3 Aug 2026
- 2026Fuzzy PyTorch: Rapid Numerical Variability Evaluation for Deep Learning Models25 May 2026
- 2026Embodied Foundation Models at the Edge: A Survey of Deployment Constraints and Mitigation Strategies16 Mar 2026
- 2026Optimizing Tensor Train Decomposition in DNNs for RISC-V Architectures Using Design Space Exploration and Compiler Optimizations2 Feb 2026
- 2025XTC, A Research Platform for Optimizing AI Workload Operators18 Dec 2025
- 2025Ariel-ML: Computing Parallelization with Embedded Rust for Neural Networks on Heterogeneous Multi-core Microcontrollers10 Dec 2025
- 2025A High-Level Compiler Integration Approach for Deep Learning Accelerators Supporting Abstraction and Optimization7 Jul 2025
- 2025Fake Runs, Real Fixes -- Analyzing xPU Performance Through Simulation18 Mar 2025
- 2024MATCH: Model-Aware TVM-based Compilation for Heterogeneous Edge Devices11 Oct 2024
- 2024Full-stack evaluation of Machine Learning inference workloads for RISC-V systems24 May 2024
- 2022Productive Reproducible Workflows for DNNs: A Case Study for Industrial Defect Detection19 Jun 2022