MicroEvo: Knowledge-Guided LLM Sampling for Efficient Microarchitecture Design Space Exploration
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Abstract (arXiv)
Microarchitecture design space exploration suffers from expansive search spaces and expensive PPA evaluation, leaving only a small simulation budget for design decision-making. Existing methods perform blind search without considering microarchitectural dependencies and fail to learn from the iterative search effectively, leading to wasted evaluations and weak Pareto convergence. In this paper, we propose MicroEvo, a knowledge-guided framework that couples off-the-shelf LLMs with Monte Carlo Tree Search (MCTS) for multi-objective microarchitecture optimization. MicroEvo combines LLM-driven evolutionary operators, a Pareto-aware tree policy that balances Pareto contribution and diversity, an active knowledge accumulation mechanism that extracts and reuses optimization insights, and state-aware directives that adapt the search behavior online. Experiments show that MicroEvo improves Pareto-front quality by up to 36.2% over NSGA-II and achieves 10.6x higher search efficiency, and also demonstrates strong scalability to a complex industrial-scale core. The code repository is available at: https://github.com/GEAR-SEU/MicroEvo-ICCAD-26.
Key facts. Cited by 1 paper in the map (data through 7 Oct 2026). Builds on 10 of its 38 references that are in the map. First posted on arXiv 6 Aug 2026.
Builds on
10 of 38 references.
References · 10
- 2024ReEvo: Large Language Models as Hyper-Heuristics with Reflective Evolutioncited by 266
- 2021Monte Carlo Tree Search: A Review of Recent Modifications and Applicationscited by 158
- 2025Monte Carlo Tree Search for Comprehensive Exploration in LLM-Based Automatic Heuristic Designcited by 100
- 2024Evolutionary Computation in the Era of Large Language Model: Survey and Roadmapcited by 89
- 2025HiFo-Prompt: Prompting with Hindsight and Foresight for LLM-based Automatic Heuristic Designcited by 13
- 2025FIXME: Towards End-to-End Benchmarking of LLM-Aided Design Verificationcited by 9
- 2025iDSE: Navigating Design Space Exploration in High-Level Synthesis Using LLMscited by 6
- 2025ChatHLS: Towards Systematic Design Automation and Optimization for High-Level Synthesiscited by 6
- 2026ChatSVA: Bridging SVA Generation for Hardware Verification via Task-Specific LLMscited by 5
- 2025ChipMind: Retrieval-Augmented Reasoning for Long-Context Circuit Design Specificationscited by 3
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Citing papers per year: 2026: 1.
1 paper.
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