FIXME: Towards End-to-End Benchmarking of LLM-Aided Design Verification
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Abstract (arXiv)
Despite the transformative potential of Large Language Models (LLMs) in hardware design, a comprehensive evaluation of their capabilities in design verification remains underexplored. Current efforts predominantly focus on RTL generation and basic debugging, overlooking the critical domain of functional verification, which is the primary bottleneck in modern design methodologies due to the rapid escalation of hardware complexity. We present FIXME, the first end-to-end, multi-model, and open-source evaluation framework for assessing LLM performance in hardware functional verification (FV) to address this crucial gap. FIXME introduces a structured three-level difficulty hierarchy spanning six verification sub-domains and 180 diverse tasks, enabling in-depth analysis across the design lifecycle. Leveraging a collaborative AI-human approach, we construct a high-quality dataset using 100% silicon-proven designs, ensuring comprehensive coverage of real-world challenges. Furthermore, we enhance the functional coverage by 45.57% through expert-guided optimization. By rigorously evaluating state-of-the-art LLMs such as GPT-4, Claude3, and LlaMA3, we identify key areas for improvement and outline promising research directions to unlock the full potential of LLM-driven automation in hardware design verification. The benchmark is available at https://github.com/ChatDesignVerification/FIXME.
Key facts. Cited by 9 papers in the map (data through 7 Oct 2026). First posted on arXiv 6 Jul 2025.
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Citing papers per year: 2025: 2; 2026: 7.
9 papers.
- 2025Revolution or Hype? Seeking the Limits of Large Models in Hardware Designcited by 9
- 2026ChatSVA: Bridging SVA Generation for Hardware Verification via Task-Specific LLMscited by 5
- 2025ChipMind: Retrieval-Augmented Reasoning for Long-Context Circuit Design Specificationscited by 3
- 2026Agentic Agile-V: From Vibe Coding to Verified Engineering in Software and Hardware Developmentcited by 2
- 2026RefEvo: Agentic Design with Co-Evolutionary Verification for Agile Reference Model Generationcited by 1
- 2026HAVEN: Hybrid Automated Verification ENgine for UVM Testbench Synthesis with LLMscited by 1
- 2026MicroEvo: Knowledge-Guided LLM Sampling for Efficient Microarchitecture Design Space Explorationcited by 1
- 2026CiteRadar: A Citation Intelligence Platform for Researcher Profiling and Geographic Visualizationcited by 0
- 2026TokenPowerSandbox: Evidence-Gated CPU-First Screening for Energy-Aware LLM Servingcited by 0
- 2026TokenPowerSandbox: Evidence-Gated CPU-First Screening for Energy-Aware LLM Serving11 Aug 2026
- 2026MicroEvo: Knowledge-Guided LLM Sampling for Efficient Microarchitecture Design Space Exploration6 Aug 2026
- 2026Agentic Agile-V: From Vibe Coding to Verified Engineering in Software and Hardware Development19 May 2026
- 2026HAVEN: Hybrid Automated Verification ENgine for UVM Testbench Synthesis with LLMs30 Apr 2026
- 2026CiteRadar: A Citation Intelligence Platform for Researcher Profiling and Geographic Visualization27 Apr 2026
- 2026RefEvo: Agentic Design with Co-Evolutionary Verification for Agile Reference Model Generation27 Apr 2026
- 2026ChatSVA: Bridging SVA Generation for Hardware Verification via Task-Specific LLMs3 Apr 2026
- 2025ChipMind: Retrieval-Augmented Reasoning for Long-Context Circuit Design Specifications5 Dec 2025
- 2025Revolution or Hype? Seeking the Limits of Large Models in Hardware Design5 Sep 2025