mlsanityData to 14 Oct 2026

FLARE: One-Shot PE-Level Fault Localization in Systolic Arrays via Algebraic Test Vectors

arXiv 2605.08594 ↗First posted 9 May 2026cs.AR cs.IT cs.LGcited by 1

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Abstract (arXiv)

Systolic arrays are the dominant compute fabric for neural network inference. Prior work has addressed column-level fault detection efficiently with uniform test patterns, but row-level (PE-level) fault localization within a faulty column remains open without resorting to hardware redundancy. The fundamental obstacle is that uniform test inputs destroy per-row signatures: any test that activates every row equally cannot distinguish which row is the source of an observed deviation. In this paper, we propose a lightweight, purely algorithmic remedy based on coprime test vectors. By assigning pairwise coprime integers as test-input entries, a permanent weight-register fault produces a deviation whose divisibility signature uniquely identifies the faulty row. Under a general bounded error model, a single test pass localizes the faulty row with high probability. This error model covers a broader class of faults than what prior dataflow-aware testing work has primarily emphasized. When one round is insufficient, a second pass using a ratio computation achieves exact localization; for the special case of single-bit errors, odd coprime entries guarantee exact localization in one round. For INT16 arithmetic, a single test pass covers array sizes up to 256×256 with localization probability above 0.98, at a test cost under 1% of one inference GEMM tile.

Key facts. Cited by 1 paper in the map (data through 14 Oct 2026). Builds on 15 of its 51 references that are in the map. First posted on arXiv 9 May 2026.

Builds on

15 of 51 references.

References · 15

  1. 2019Terminal Brain Damage: Exposing the Graceless Degradation in Deep Neural Networks Under Hardware Fault Attackscited by 57
  2. 2019FT-ClipAct: Resilience Analysis of Deep Neural Networks and Improving their Fault Tolerance using Clipped Activationcited by 31
  3. 2018Analyzing and Mitigating the Impact of Permanent Faults on a Systolic Array Based Neural Network Acceleratorcited by 25
  4. 2021Silent Data Corruptions at Scalecited by 23
  5. 2025SCALE-Sim v3: A modular cycle-accurate systolic accelerator simulator for end-to-end system analysiscited by 9
  6. 2023A Low-cost Strategic Monitoring Approach for Scalable and Interpretable Error Detection in Deep Neural Networkscited by 6
  7. 2023BERRY: Bit Error Robustness for Energy-Efficient Reinforcement Learning-Based Autonomous Systemscited by 5
  8. 2024SAFFIRA: a Framework for Assessing the Reliability of Systolic-Array-Based DNN Acceleratorscited by 5
  9. 2025ReaLM: Reliable and Efficient Large Language Model Inference with Statistical Algorithm-Based Fault Tolerancecited by 5
  10. 2023ApproxABFT: Approximate Algorithm-Based Fault Tolerance for Neural Network Processingcited by 3
  11. 2023ALBERTA: ALgorithm-Based Error Resilience in Transformer Architecturescited by 3
  12. 2025CogSys: Efficient and Scalable Neurosymbolic Cognition System via Algorithm-Hardware Co-Designcited by 3
3 more
  1. 2024PVF:Understanding AI Vulnerability Against SDCscited by 2
  2. 2025FORTALESA: Fault-Tolerant Reconfigurable Systolic Array for DNN Inferencecited by 1
  3. 2025Periodic Online Testing for Sparse Systolic Tensor Arrayscited by 1

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