CogSys: Efficient and Scalable Neurosymbolic Cognition System via Algorithm-Hardware Co-Design
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Abstract (arXiv)
Neurosymbolic AI is an emerging compositional paradigm that fuses neural learning with symbolic reasoning to enhance the transparency, interpretability, and trustworthiness of AI. It also exhibits higher data efficiency making it promising for edge deployments. Despite the algorithmic promises and demonstrations, unfortunately executing neurosymbolic workloads on current hardware (CPU/GPU/TPU) is challenging due to higher memory intensity, greater compute heterogeneity and access pattern irregularity, leading to severe hardware underutilization. This work proposes CogSys, a characterization and co-design framework dedicated to neurosymbolic AI system acceleration, aiming to win both reasoning efficiency and scalability. On the algorithm side, CogSys proposes an efficient factorization technique to alleviate compute and memory overhead. On the hardware side, CogSys proposes a scalable neurosymbolic architecture with reconfigurable neuro/symbolic processing elements (nsPE) and bubble streaming (BS) dataflow with spatial-temporal (ST) mapping for highly parallel and efficient neurosymbolic computation. On the system side, CogSys features an adaptive workload-aware scheduler (adSCH) to orchestrate heterogeneous kernels and enhance resource utilization. Evaluated across cognitive workloads, CogSys enables reconfigurable support for neural and symbolic kernels and exhibits >75x speedup over TPU-like systolic array with only <5% area overhead, as benchmarked under the TSMC 28nm technology node. CogSys achieves 4x-96x speedup compared to desktop and edge GPUs. For the first time, CogSys enables real-time abduction reasoning towards human fluid intelligence, requiring only 0.3 s per reasoning task with 4 mm2 area and 1.48 W power consumption.
Key facts. Cited by 3 papers in the map (data through 14 Oct 2026). First posted on arXiv 3 Mar 2025.
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Citing papers per year: 2025: 1; 2026: 2.
3 papers.
- 2025NSFlow: An End-to-End FPGA Framework with Scalable Dataflow Architecture for Neuro-Symbolic AIcited by 1
- 2026FLARE: One-Shot PE-Level Fault Localization in Systolic Arrays via Algebraic Test Vectorscited by 1
- 2026REASON: Accelerating Probabilistic Logical Reasoning for Scalable Neuro-Symbolic Intelligencecited by 0
- 2026FLARE: One-Shot PE-Level Fault Localization in Systolic Arrays via Algebraic Test Vectors9 May 2026
- 2026REASON: Accelerating Probabilistic Logical Reasoning for Scalable Neuro-Symbolic Intelligence28 Jan 2026
- 2025NSFlow: An End-to-End FPGA Framework with Scalable Dataflow Architecture for Neuro-Symbolic AI27 Apr 2025