HTVM: Efficient Neural Network Deployment On Heterogeneous TinyML Platforms
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Abstract (arXiv)
Optimal deployment of deep neural networks (DNNs) on state-of-the-art Systems-on-Chips (SoCs) is crucial for tiny machine learning (TinyML) at the edge. The complexity of these SoCs makes deployment non-trivial, as they typically contain multiple heterogeneous compute cores with limited, programmer-managed memory to optimize latency and energy efficiency. We propose HTVM - a compiler that merges TVM with DORY to maximize the utilization of heterogeneous accelerators and minimize data movements. HTVM allows deploying the MLPerf(TM) Tiny suite on DIANA, an SoC with a RISC-V CPU, and digital and analog compute-in-memory AI accelerators, at 120x improved performance over plain TVM deployment.
Key facts. Cited by 3 papers in the map (data through 14 Oct 2026). First posted on arXiv 11 Jun 2024.
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Citing papers per year: 2024: 1; 2025: 1; 2026: 1.
3 papers.
- 2024MATCH: Model-Aware TVM-based Compilation for Heterogeneous Edge Devicescited by 5
- 2025An Open-Source HW-SW Co-Development Framework Enabling Efficient Multi-Accelerator Systemscited by 2
- 2026MATCHA: Efficient Deployment of Deep Neural Networks on Multi-Accelerator Heterogeneous Edge SoCscited by 0
- 2026MATCHA: Efficient Deployment of Deep Neural Networks on Multi-Accelerator Heterogeneous Edge SoCs10 Apr 2026
- 2025An Open-Source HW-SW Co-Development Framework Enabling Efficient Multi-Accelerator Systems20 Aug 2025
- 2024MATCH: Model-Aware TVM-based Compilation for Heterogeneous Edge Devices11 Oct 2024