MenTeR: A fully-automated Multi-agenT workflow for end-to-end RF/Analog Circuits Netlist Design
Not on the map. Why?
Abstract (arXiv)
RF/Analog design is essential for bridging digital technologies with real-world signals, ensuring the functionality and reliability of a wide range of electronic systems. However, analog design procedures are often intricate, time-consuming and reliant on expert intuition, and hinder the time and cost efficiency of circuit development. To overcome the limitations of the manual circuit design, we introduce MenTeR - a multiagent workflow integrated into an end-to-end analog design framework. By employing multiple specialized AI agents that collaboratively address different aspects of the design process, such as specification understanding, circuit optimization, and test bench validation, MenTeR reduces the dependency on frequent trial-and-error-style intervention. MenTeR not only accelerates the design cycle time but also facilitates a broader exploration of the design space, demonstrating robust capabilities in handling real-world analog systems. We believe that MenTeR lays the groundwork for future "RF/Analog Copilots" that can collaborate seamlessly with human designers.
Key facts. Cited by 7 papers in the map (data through 14 Oct 2026). Builds on 16 of its 32 references that are in the map. First posted on arXiv 29 May 2025.
Builds on
16 of 32 references.
References · 16
- 2022Training language models to follow instructions with human feedbackcited by 15,971
- 2022Chain-of-Thought Prompting Elicits Reasoning in Large Language Modelscited by 12,459
- 2020Retrieval-Augmented Generation for Knowledge-Intensive NLP Taskscited by 9,297
- 2023Direct Preference Optimization: Your Language Model is Secretly a Reward Modelcited by 8,065
- 2023Tree of Thoughts: Deliberate Problem Solving with Large Language Modelscited by 3,211
- 2023AutoGen: Enabling Next-Gen LLM Applications via Multi-Agent Conversationcited by 1,988
- 2023MemGPT: Towards LLMs as Operating Systemscited by 1,389
- 2024SimPO: Simple Preference Optimization with a Reference-Free Rewardcited by 963
- 2023ChipNeMo: Domain-Adapted LLMs for Chip Designcited by 174
- 2023Chip-Chat: Challenges and Opportunities in Conversational Hardware Designcited by 140
- 2023Rephrase and Respond: Let Large Language Models Ask Better Questions for Themselvescited by 123
- 2024AnalogCoder: Analog Circuit Design via Training-Free Code Generationcited by 84
4 more
- 2024Adaptive In-conversation Team Building for Language Model Agentscited by 39
- 2024AmpAgent: An LLM-based Multi-Agent System for Multi-stage Amplifier Schematic Design from Literature for Process and Performance Portingcited by 29
- 2024LayoutCopilot: An LLM-powered Multi-agent Collaborative Framework for Interactive Analog Layout Designcited by 25
- 2024AMSnet-KG: A Netlist Dataset for LLM-based AMS Circuit Auto-Design Using Knowledge Graph RAGcited by 16
Built on by
Citing papers per year: 2025: 1; 2026: 6.
7 papers.
- 2025HeaRT: A Hierarchical Circuit Reasoning Tree-Based Agentic Framework for AMS Design Optimizationcited by 5
- 2026CircuitLM: A Multi-Agent LLM-Aided Design Framework for Generating Circuit Schematics from Natural Language Promptscited by 4
- 2026RF-Agent: A Practical Framework for Building Language Agents for RFIC Designcited by 1
- 2026TOPCELL: Topology Optimization of Standard Cell via LLMscited by 0
- 2026Agentic Electronic Design Automation: A Handoff Perspectivecited by 0
- 2026AaLLM: An End-to-End Analog Circuit Design Framework from Topology Generation to Sizing Using Large Language Modelscited by 0
- 2026CktHGVAE: A Symmetric Design/State Heterogeneous Graph Variational Autoencoder for Transistor-level Analog/Mixed-signal Circuit Design and Analysiscited by 0
- 2026CktHGVAE: A Symmetric Design/State Heterogeneous Graph Variational Autoencoder for Transistor-level Analog/Mixed-signal Circuit Design and Analysis14 Oct 2026
- 2026AaLLM: An End-to-End Analog Circuit Design Framework from Topology Generation to Sizing Using Large Language Models13 Aug 2026
- 2026RF-Agent: A Practical Framework for Building Language Agents for RFIC Design21 Jul 2026
- 2026Agentic Electronic Design Automation: A Handoff Perspective18 Jun 2026
- 2026TOPCELL: Topology Optimization of Standard Cell via LLMs15 Apr 2026
- 2026CircuitLM: A Multi-Agent LLM-Aided Design Framework for Generating Circuit Schematics from Natural Language Prompts8 Jan 2026
- 2025HeaRT: A Hierarchical Circuit Reasoning Tree-Based Agentic Framework for AMS Design Optimization24 Nov 2025