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Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation

arXiv 2510.10676 ↗First posted 12 Oct 2025cs.AR cs.CL cs.ROcited by 0

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Abstract (arXiv)

This paper introduces Bhasha-Rupantarika, a light and efficient multilingual translation system tailored through algorithm-hardware codesign for resource-limited settings. The method investigates model deployment at sub-octet precision levels (FP8, INT8, INT4, and FP4), with experimental results indicating a 4.1x reduction in model size (FP4) and a 4.2x speedup in inference speed, which correlates with an increased throughput of 66 tokens/s (improvement by 4.8x). This underscores the importance of ultra-low precision quantization for real-time deployment in IoT devices using FPGA accelerators, achieving performance on par with expectations. Our evaluation covers bidirectional translation between Indian and international languages, showcasing its adaptability in low-resource linguistic contexts. The FPGA deployment demonstrated a 1.96x reduction in LUTs and a 1.65x decrease in FFs, resulting in a 2.2x enhancement in throughput compared to OPU and a 4.6x enhancement compared to HPTA. Overall, the evaluation provides a viable solution based on quantisation-aware translation along with hardware efficiency suitable for deployable multilingual AI systems. The entire codes [https://github.com/mukullokhande99/Bhasha-Rupantarika/] and dataset for reproducibility are publicly available, facilitating rapid integration and further development by researchers.

Key facts. No citing papers in the map yet (data through 7 Oct 2026). Builds on 17 of its 49 references that are in the map. First posted on arXiv 12 Oct 2025.

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References · 17

  1. 2022Robust Speech Recognition via Large-Scale Weak Supervisioncited by 3,972
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  12. 2021ShortcutFusion: From Tensorflow to FPGA-based accelerator with reuse-aware memory allocation for shortcut datacited by 6
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  2. 2025Occamy: A 432-Core Dual-Chiplet Dual-HBM2E 768-DP-GFLOP/s RISC-V System for 8-to-64-bit Dense and Sparse Computing in 12nm FinFETcited by 3
  3. 2025XR-NPE: High-Throughput Mixed-precision SIMD Neural Processing Engine for Extended Reality Perception Workloadscited by 3
  4. 2025QForce-RL: Quantized FPGA-Optimized Reinforcement Learning Compute Enginecited by 2
  5. 2023SelfSeg: A Self-supervised Sub-word Segmentation Method for Neural Machine Translationcited by 1

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