XR-NPE: High-Throughput Mixed-precision SIMD Neural Processing Engine for Extended Reality Perception Workloads
Not on the map. Why?
Abstract (arXiv)
This work proposes XR-NPE, a high-throughput Mixed-precision SIMD Neural Processing Engine, designed for extended reality (XR) perception workloads like visual inertial odometry (VIO), object classification, and eye gaze extraction. XR-NPE is first to support FP4, Posit (4,1), Posit (8,0), and Posit (16,1) formats, with layer adaptive hybrid-algorithmic implementation supporting ultra-low bit precision to significantly reduce memory bandwidth requirements, and accompanied by quantization-aware training for minimal accuracy loss. The proposed Reconfigurable Mantissa Multiplication and Exponent processing Circuitry (RMMEC) reduces dark silicon in the SIMD MAC compute engine, assisted by selective power gating to reduce energy consumption, providing 2.85x improved arithmetic intensity. XR-NPE achieves a maximum operating frequency of 1.72 GHz, area 0.016 mm2 , and arithmetic intensity 14 pJ at CMOS 28nm, reducing 42% area, 38% power compared to the best of state-of-the-art MAC approaches. The proposed XR-NPE based AXI-enabled Matrix-multiplication co-processor consumes 1.4x fewer LUTs, 1.77x fewer FFs, and provides 1.2x better energy efficiency compared to SoTA accelerators on VCU129. The proposed co-processor provides 23% better energy efficiency and 4% better compute density for VIO workloads. XR-NPE establishes itself as a scalable, precision-adaptive compute engine for future resource-constrained XR devices. The complete set for codes for results reproducibility are released publicly, enabling designers and researchers to readily adopt and build upon them. https://github.com/mukullokhande99/XR-NPE.
Key facts. Cited by 3 papers in the map (data through 7 Oct 2026). Builds on 7 of its 35 references that are in the map. First posted on arXiv 18 Aug 2025.
Builds on
7 of 35 references.
References · 7
- 2024Flex-PE: Flexible and SIMD Multi-Precision Processing Element for AI Workloadscited by 15
- 2023Marsellus: A Heterogeneous RISC-V AI-IoT End-Node SoC with 2-to-8b DNN Acceleration and 30%-Boost Adaptive Body Biasingcited by 8
- 2023Cheshire: A Lightweight, Linux-Capable RISC-V Host Platform for Domain-Specific Accelerator Plug-Incited by 7
- 2023Low-Precision Mixed-Computation Models for Inference on Edgecited by 4
- 2025Maestro: A 302 GFLOPS/W and 19.8GFLOPS RISC-V Vector-Tensor Architecture for Wearable Ultrasound Edge Computingcited by 4
- 2024UL-VIO: Ultra-lightweight Visual-Inertial Odometry with Noise Robust Test-time Adaptationcited by 3
- 2025Occamy: A 432-Core Dual-Chiplet Dual-HBM2E 768-DP-GFLOP/s RISC-V System for 8-to-64-bit Dense and Sparse Computing in 12nm FinFETcited by 3
Built on by
Citing papers per year: 2025: 1; 2026: 2.
3 papers.
- 2026SPADE: A SIMD Posit-enabled compute engine for Accelerating DNN Efficiencycited by 1
- 2026CORVET: A CORDIC-Powered, Resource-Frugal Mixed-Precision Vector Processing Engine for High-Throughput AIoT applicationscited by 1
- 2025Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translationcited by 0
- 2026CORVET: A CORDIC-Powered, Resource-Frugal Mixed-Precision Vector Processing Engine for High-Throughput AIoT applications22 Feb 2026
- 2026SPADE: A SIMD Posit-enabled compute engine for Accelerating DNN Efficiency24 Jan 2026
- 2025Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation12 Oct 2025