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OPTIMA: Design-Space Exploration of Discharge-Based In-SRAM Computing: Quantifying Energy-Accuracy Trade-Offs

arXiv 2411.06846 ↗First posted 11 Nov 2024cs.AR cs.PFcited by 0

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Abstract (arXiv)

In-SRAM computing promises energy efficiency, but circuit nonlinearities and PVT variations pose major challenges in designing robust accelerators. To address this, we introduce OPTIMA, a modeling framework that aids in analyzing bit-line discharge and power consumption in 6T-SRAM-based accelerators. It provides insights into limiting factors and enables fast design-space exploration of circuit configurations. Leveraging OPTIMA for in-SRAM multiplications exhibits ~100x simulation speed-up while maintaining an RMS modeling error of 0.88mV. Exploration yields an optimized multiplier with 1.05pJ energy consumption per 4-bit operation and classification accuracies of 71.8% (top-1) and 90.4% (top-5) for ImageNet and 92.5% for CIFAR-10 datasets respectively when applied in quantized DNNs. To further support research and development, we made our tool flow available open source at https://github.com/sevjaeg/optima.

Key facts. No citing papers in the map yet (data through 14 Oct 2026). Builds on 7 of its 24 references that are in the map. First posted on arXiv 11 Nov 2024.

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7 of 24 references.

References · 7

  1. 2015Deep Residual Learning for Image Recognitioncited by 52,096
  2. 2014Very Deep Convolutional Networks for Large-Scale Image Recognitioncited by 15,364
  3. 2018Neural Cache: Bit-Serial In-Cache Acceleration of Deep Neural Networkscited by 32
  4. 2021CAP-RAM: A Charge-Domain In-Memory Computing 6T-SRAM for Accurate and Precision-Programmable CNN Inferencecited by 5
  5. 2020IMAC: In-memory multi-bit Multiplication andACcumulation in 6T SRAM Arraycited by 4
  6. 2022AID: Accuracy Improvement of Analog Discharge-Based in-SRAM Multiplication Acceleratorcited by 1
  7. 2022SMART: Investigating the Impact of Threshold Voltage Suppression in an In-SRAM Multiplication/Accumulation Accelerator for Accuracy Improvement in 65 nm CMOS Technologycited by 1

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  6. 2026TRAPTI: Time-Resolved Analysis for SRAM Banking and Power Gating Optimization in Embedded Transformer Inference ↗
  7. 2022A Charge Domain P-8T SRAM Compute-In-Memory with Low-Cost DAC/ADC Operation for 4-bit Input Processing
  8. 2026TOM: A Ternary Read-only Memory Accelerator for LLM-powered Edge Intelligence