mlsanityData to 14 Oct 2026

A 65nm 8b-Activation 8b-Weight SRAM-Based Charge-Domain Computing-in-Memory Macro Using A Fully-Parallel Analog Adder Network and A Single-ADC Interface

arXiv 2212.04320 ↗First posted 23 Nov 2022cs.AR cs.LGcited by 0

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Abstract (arXiv)

Performing data-intensive tasks in the von Neumann architecture is challenging to achieve both high performance and power efficiency due to the memory wall bottleneck. Computing-in-memory (CiM) is a promising mitigation approach by enabling parallel in-situ multiply-accumulate (MAC) operations within the memory with support from the peripheral interface and datapath. SRAM-based charge-domain CiM (CD-CiM) has shown its potential of enhanced power efficiency and computing accuracy. However, existing SRAM-based CD-CiM faces scaling challenges to meet the throughput requirement of high-performance multi-bit-quantization applications. This paper presents an SRAM-based high-throughput ReLU-optimized CD-CiM macro. It is capable of completing MAC and ReLU of two signed 8b vectors in one CiM cycle with only one A/D conversion. Along with non-linearity compensation for the analog computing and A/D conversion interfaces, this work achieves 51.2GOPS throughput and 10.3TOPS/W energy efficiency, while showing 88.6% accuracy in the CIFAR-10 dataset.

Key facts. No citing papers in the map yet (data through 14 Oct 2026). Builds on 1 of its 9 references that are in the map. First posted on arXiv 23 Nov 2022.

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References · 1

  1. 2021Mitigating Adversarial Attack for Compute-in-Memory Accelerator Utilizing On-chip Finetunecited by 1

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  1. 2022A Charge Domain P-8T SRAM Compute-In-Memory with Low-Cost DAC/ADC Operation for 4-bit Input Processing
  2. 2024ASiM: Modeling and Analyzing Inference Accuracy of SRAM-Based Analog CiM Circuits
  3. 2025A Novel 8T SRAM-Based In-Memory Computing Architecture for MAC-Derived Logical Functions ↗
  4. 2026A Reconfigurable Computing In-Memory Macro with Charge-sharing-based Weighted Accumulator ↗
  5. 2026NOVA-CIM: Noise- and Correlation-Tolerant Stochastic Interfaces for Analog Compute-in-Memory
  6. 2021PR-CIM: a Variation-Aware Binary-Neural-Network Framework for Process-Resilient Computation-in-memory
  7. 2026Time--to--Digital Converter (TDC)--Based Resonant Compute--in--Memory for INT8 CNNs with Layer--Optimized SRAM Mapping
  8. 2021CAP-RAM: A Charge-Domain In-Memory Computing 6T-SRAM for Accurate and Precision-Programmable CNN Inference