mlsanityData to 14 Oct 2026

CAP-RAM: A Charge-Domain In-Memory Computing 6T-SRAM for Accurate and Precision-Programmable CNN Inference

arXiv 2107.02388 ↗First posted 6 Jul 2021cs.AR cs.ET cs.LGcited by 5

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Abstract (arXiv)

A compact, accurate, and bitwidth-programmable in-memory computing (IMC) static random-access memory (SRAM) macro, named CAP-RAM, is presented for energy-efficient convolutional neural network (CNN) inference. It leverages a novel charge-domain multiply-and-accumulate (MAC) mechanism and circuitry to achieve superior linearity under process variations compared to conventional IMC designs. The adopted semi-parallel architecture efficiently stores filters from multiple CNN layers by sharing eight standard 6T SRAM cells with one charge-domain MAC circuit. Moreover, up to six levels of bit-width of weights with two encoding schemes and eight levels of input activations are supported. A 7-bit charge-injection SAR (ciSAR) analog-to-digital converter (ADC) getting rid of sample and hold (S&H) and input/reference buffers further improves the overall energy efficiency and throughput. A 65-nm prototype validates the excellent linearity and computing accuracy of CAP-RAM. A single 512x128 macro stores a complete pruned and quantized CNN model to achieve 98.8% inference accuracy on the MNIST data set and 89.0% on the CIFAR-10 data set, with a 573.4-giga operations per second (GOPS) peak throughput and a 49.4-tera operations per second (TOPS)/W energy efficiency.

Key facts. Cited by 5 papers in the map (data through 14 Oct 2026). Builds on 5 of its 36 references that are in the map. First posted on arXiv 6 Jul 2021.

Builds on

5 of 36 references.

References · 5

  1. 2015Deep Residual Learning for Image Recognitioncited by 52,096
  2. 2014Going Deeper with Convolutionscited by 4,241
  3. 2016XNOR-Net: ImageNet Classification Using Binary Convolutional Neural Networkscited by 849
  4. 2018ADMM-NN: An Algorithm-Hardware Co-Design Framework of DNNs Using Alternating Direction Method of Multiplierscited by 42
  5. 2018A Microprocessor implemented in 65nm CMOS with Configurable and Bit-scalable Accelerator for Programmable In-memory Computingcited by 1

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Cited by year (2026 to 14 Oct)

Citing papers per year: 2022: 1; 2023: 1; 2024: 2; 2025: 0; 2026: 1.

5 papers.

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  1. 2024ASiM: Modeling and Analyzing Inference Accuracy of SRAM-Based Analog CiM Circuits
  2. 2025A Hybrid-Domain Floating-Point Compute-in-Memory Architecture for Efficient Acceleration of High-Precision Deep Neural Networks ↗
  3. 2023EnforceSNN: Enabling Resilient and Energy-Efficient Spiking Neural Network Inference considering Approximate DRAMs for Embedded Systems
  4. 2025A Novel 8T SRAM-Based In-Memory Computing Architecture for MAC-Derived Logical Functions ↗
  5. 2023ReDy: A Novel ReRAM-centric Dynamic Quantization Approach for Energy-efficient CNN Inference
  6. 2022A 65nm 8b-Activation 8b-Weight SRAM-Based Charge-Domain Computing-in-Memory Macro Using A Fully-Parallel Analog Adder Network and A Single-ADC Interface
  7. 2025NeuroSim V1.5: Improved Software Backbone for Benchmarking Compute-in-Memory Accelerators with Device and Circuit-level Non-idealities
  8. 2025Rapid yet accurate Tile-circuit and device modeling for Analog In-Memory Computing