CAP-RAM: A Charge-Domain In-Memory Computing 6T-SRAM for Accurate and Precision-Programmable CNN Inference
Not on the map. Why?
Abstract (arXiv)
A compact, accurate, and bitwidth-programmable in-memory computing (IMC) static random-access memory (SRAM) macro, named CAP-RAM, is presented for energy-efficient convolutional neural network (CNN) inference. It leverages a novel charge-domain multiply-and-accumulate (MAC) mechanism and circuitry to achieve superior linearity under process variations compared to conventional IMC designs. The adopted semi-parallel architecture efficiently stores filters from multiple CNN layers by sharing eight standard 6T SRAM cells with one charge-domain MAC circuit. Moreover, up to six levels of bit-width of weights with two encoding schemes and eight levels of input activations are supported. A 7-bit charge-injection SAR (ciSAR) analog-to-digital converter (ADC) getting rid of sample and hold (S&H) and input/reference buffers further improves the overall energy efficiency and throughput. A 65-nm prototype validates the excellent linearity and computing accuracy of CAP-RAM. A single 512x128 macro stores a complete pruned and quantized CNN model to achieve 98.8% inference accuracy on the MNIST data set and 89.0% on the CIFAR-10 data set, with a 573.4-giga operations per second (GOPS) peak throughput and a 49.4-tera operations per second (TOPS)/W energy efficiency.
Key facts. Cited by 5 papers in the map (data through 14 Oct 2026). Builds on 5 of its 36 references that are in the map. First posted on arXiv 6 Jul 2021.
Builds on
5 of 36 references.
References · 5
- 2015Deep Residual Learning for Image Recognitioncited by 52,096
- 2014Going Deeper with Convolutionscited by 4,241
- 2016XNOR-Net: ImageNet Classification Using Binary Convolutional Neural Networkscited by 849
- 2018ADMM-NN: An Algorithm-Hardware Co-Design Framework of DNNs Using Alternating Direction Method of Multiplierscited by 42
- 2018A Microprocessor implemented in 65nm CMOS with Configurable and Bit-scalable Accelerator for Programmable In-memory Computingcited by 1
Built on by
Citing papers per year: 2022: 1; 2023: 1; 2024: 2; 2025: 0; 2026: 1.
5 papers.
- 2023YOCO: A Hybrid In-Memory Computing Architecture with 8-bit Sub-PetaOps/W In-Situ Multiply Arithmetic for Large-Scale AIcited by 1
- 2022A Charge Domain P-8T SRAM Compute-In-Memory with Low-Cost DAC/ADC Operation for 4-bit Input Processingcited by 0
- 2024Approximate ADCs for In-Memory Computingcited by 0
- 2024OPTIMA: Design-Space Exploration of Discharge-Based In-SRAM Computing: Quantifying Energy-Accuracy Trade-Offscited by 0
- 2026You Only Charge Once 2.0 : A End-to-End Analog Computing-in-Memory Architecture with Reconfigurable Switched Capacitorscited by 0
- 2026You Only Charge Once 2.0 : A End-to-End Analog Computing-in-Memory Architecture with Reconfigurable Switched Capacitors11 Aug 2026
- 2024OPTIMA: Design-Space Exploration of Discharge-Based In-SRAM Computing: Quantifying Energy-Accuracy Trade-Offs11 Nov 2024
- 2024Approximate ADCs for In-Memory Computing11 Aug 2024
- 2023YOCO: A Hybrid In-Memory Computing Architecture with 8-bit Sub-PetaOps/W In-Situ Multiply Arithmetic for Large-Scale AI19 Dec 2023
- 2022A Charge Domain P-8T SRAM Compute-In-Memory with Low-Cost DAC/ADC Operation for 4-bit Input Processing29 Nov 2022
Similar, not cited
Close in wording, no citation either way
- 2024ASiM: Modeling and Analyzing Inference Accuracy of SRAM-Based Analog CiM Circuits
- 2025A Hybrid-Domain Floating-Point Compute-in-Memory Architecture for Efficient Acceleration of High-Precision Deep Neural Networks ↗
- 2023EnforceSNN: Enabling Resilient and Energy-Efficient Spiking Neural Network Inference considering Approximate DRAMs for Embedded Systems
- 2025A Novel 8T SRAM-Based In-Memory Computing Architecture for MAC-Derived Logical Functions ↗
- 2023ReDy: A Novel ReRAM-centric Dynamic Quantization Approach for Energy-efficient CNN Inference
- 2022A 65nm 8b-Activation 8b-Weight SRAM-Based Charge-Domain Computing-in-Memory Macro Using A Fully-Parallel Analog Adder Network and A Single-ADC Interface
- 2025NeuroSim V1.5: Improved Software Backbone for Benchmarking Compute-in-Memory Accelerators with Device and Circuit-level Non-idealities
- 2025Rapid yet accurate Tile-circuit and device modeling for Analog In-Memory Computing