mlsanityData to 13 Oct 2026

BARVINN: Arbitrary Precision DNN Accelerator Controlled by a RISC-V CPU

arXiv 2301.00290 ↗First posted 31 Dec 2022cs.ARcited by 6

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Abstract (arXiv)

We present a DNN accelerator that allows inference at arbitrary precision with dedicated processing elements that are configurable at the bit level. Our DNN accelerator has 8 Processing Elements controlled by a RISC-V controller with a combined 8.2 TMACs of computational power when implemented with the recent Alveo U250 FPGA platform. We develop a code generator tool that ingests CNN models in ONNX format and generates an executable command stream for the RISC-V controller. We demonstrate the scalable throughput of our accelerator by running different DNN kernels and models when different quantization levels are selected. Compared to other low precision accelerators, our accelerator provides run time programmability without hardware reconfiguration and can accelerate DNNs with multiple quantization levels, regardless of the target FPGA size. BARVINN is an open source project and it is available at https://github.com/hossein1387/BARVINN.

Key facts. Cited by 6 papers in the map (data through 13 Oct 2026). Builds on 11 of its 23 references that are in the map. First posted on arXiv 31 Dec 2022.

Builds on

11 of 23 references.

References · 11

  1. 2015Deep Residual Learning for Image Recognitioncited by 51,950
  2. 2017Mixed Precision Trainingcited by 1,147
  3. 2019Learned Step Size Quantizationcited by 621
  4. 2018HAQ: Hardware-Aware Automated Quantization with Mixed Precisioncited by 439
  5. 2016Quantized Neural Networks: Training Neural Networks with Low Precision Weights and Activationscited by 422
  6. 2016FINN: A Framework for Fast, Scalable Binarized Neural Network Inferencecited by 150
  7. 2017Bit Fusion: Bit-Level Dynamically Composable Architecture for Accelerating Deep Neural Networkscited by 109
  8. 2021Network Quantization with Element-wise Gradient Scalingcited by 86
  9. 2018FINN-R: An End-to-End Deep-Learning Framework for Fast Exploration of Quantized Neural Networkscited by 56
  10. 2019Any-Precision Deep Neural Networkscited by 40
  11. 2021Bit-Mixer: Mixed-precision networks with runtime bit-width selectioncited by 21

Built on by

Cited by year

Citing papers per year: 2023: 2; 2024: 3; 2025: 1.

6 papers.

  1. 2023A Precision-Scalable RISC-V DNN Processor with On-Device Learning Capability at the Extreme Edgecited by 11
  2. 2024Mixed-precision Neural Networks on RISC-V Cores: ISA extensions for Multi-Pumped Soft SIMD Operationscited by 5
  3. 2023Quark: An Integer RISC-V Vector Processor for Sub-Byte Quantized DNN Inferencecited by 2
  4. 2024Real-Time Spacecraft Pose Estimation Using Mixed-Precision Quantized Neural Network on COTS Reconfigurable MPSoCcited by 2
  5. 2024ARQ: A Mixed-Precision Quantization Framework for Accurate and Certifiably Robust DNNscited by 1
  6. 2025MaRVIn: A Cross-Layer Mixed-Precision RISC-V Framework for DNN Inference, from ISA Extension to Hardware Accelerationcited by 0

Similar, not cited

Close in wording, no citation either way

  1. 2024SPEED: A Scalable RISC-V Vector Processor Enabling Efficient Multi-Precision DNN Inference
  2. 2021HAO: Hardware-aware neural Architecture Optimization for Efficient Inference
  3. 2024A Scalable RISC-V Vector Processor Enabling Efficient Multi-Precision DNN Inference
  4. 2021Random and Adversarial Bit Error Robustness: Energy-Efficient and Secure DNN Accelerators
  5. 2022Design of High-Throughput Mixed-Precision CNN Accelerators on FPGA
  6. 2022BrainTTA: A 35 fJ/op Compiler Programmable Mixed-Precision Transport-Triggered NN SoC
  7. 2026PoTAcc: A Pipeline for End-to-End Acceleration of Power-of-Two Quantized DNNs
  8. 2022Hardware-Efficient Template-Based Deep CNNs Accelerator Design ↗