mlsanityData to 13 Oct 2026

BrainTTA: A 35 fJ/op Compiler Programmable Mixed-Precision Transport-Triggered NN SoC

arXiv 2211.11331 ↗First posted 21 Nov 2022cs.ARcited by 1

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Abstract (arXiv)

Recently, accelerators for extremely quantized deep neural network (DNN) inference with operand widths as low as 1-bit have gained popularity due to their ability to largely cut down energy cost per inference. In this paper, a flexible SoC with mixed-precision support is presented. Contrary to the current trend of fixed-datapath accelerators, this architecture makes use of a flexible datapath based on a Transport-Triggered Architecture (TTA). The architecture is fully programmable using C. The accelerator has a peak energy efficiency of 35/67/405 fJ/op (binary, ternary, and 8-bit precision) and a throughput of 614/307/77 GOPS, which is unprecedented for a programmable architecture.

Key facts. Cited by 1 paper in the map (data through 13 Oct 2026). Builds on 12 of its 23 references that are in the map. First posted on arXiv 21 Nov 2022.

Builds on

12 of 23 references.

References · 12

  1. 2015Deep Residual Learning for Image Recognitioncited by 51,950
  2. 2017Quantization and Training of Neural Networks for Efficient Integer-Arithmetic-Only Inferencecited by 1,585
  3. 2016Inception-v4, Inception-ResNet and the Impact of Residual Connections on Learningcited by 1,512
  4. 2018MnasNet: Platform-Aware Neural Architecture Search for Mobilecited by 941
  5. 2016XNOR-Net: ImageNet Classification Using Binary Convolutional Neural Networkscited by 849
  6. 2021A Survey of Quantization Methods for Efficient Neural Network Inferencecited by 814
  7. 2020What is the State of Neural Network Pruning?cited by 582
  8. 2019XNOR-Net++: Improved Binary Neural Networkscited by 97
  9. 2018XNOR Neural Engine: a Hardware Accelerator IP for 21.6 fJ/op Binary Neural Network Inferencecited by 30
  10. 2020CUTIE: Beyond PetaOp/s/W Ternary DNN Inference Acceleration with Better-than-Binary Energy Efficiencycited by 10
  11. 2020ChewBaccaNN: A Flexible 223 TOPS/W BNN Acceleratorcited by 9
  12. 2020Exploring Neural Networks Quantization via Layer-Wise Quantization Analysiscited by 5

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Cited by year

Citing papers per year: 2024: 1.

1 paper.

  1. 2024Advancing Neuromorphic Computing: Mixed-Signal Design Techniques Leveraging Brain Code Units and Fundamental Code Unitscited by 0

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  1. 2025A Flexible Precision Scaling Deep Neural Network Accelerator with Efficient Weight Combination
  2. 2024Mixed-precision Neural Networks on RISC-V Cores: ISA extensions for Multi-Pumped Soft SIMD Operations
  3. 2025MaRVIn: A Cross-Layer Mixed-Precision RISC-V Framework for DNN Inference, from ISA Extension to Hardware Acceleration
  4. 2023DeepBurning-MixQ: An Open Source Mixed-Precision Neural Network Accelerator Design Framework for FPGAs
  5. 2025HaShiFlex: A High-Throughput Hardened Shifter DNN Accelerator with Fine-Tuning Flexibility
  6. 2026Bitwise Systolic Array Architecture for Runtime-Reconfigurable Multi-precision Quantized Multiplication on Hardware Accelerators
  7. 2025Hardware-Aware Neural Network Compilation with Learned Optimization: A RISC-V Accelerator Approach
  8. 2023A 3 TOPS/W RISC-V Parallel Cluster for Inference of Fine-Grain Mixed-Precision Quantized Neural Networks