Hardware-efficient Residual Networks for FPGAs
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Abstract (arXiv)
Residual networks (ResNets) employ skip connections in their networks -- reusing activations from previous layers -- to improve training convergence, but these skip connections create challenges for hardware implementations of ResNets. The hardware must either wait for skip connections to be processed before processing more incoming data or buffer them elsewhere. Without skip connections, ResNets would be more hardware-efficient. Thus, we present the teacher-student learning method to gradually prune away all of a ResNet's skip connections, constructing a network we call NonResNet. We show that when implemented for FPGAs, NonResNet decreases ResNet's BRAM utilization by 9% and LUT utilization by 3% and increases throughput by 5%.
Key facts. No citing papers in the map yet (data through 14 Oct 2026). Builds on 3 of its 5 references that are in the map. First posted on arXiv 2 Feb 2021.
Builds on
3 of 5 references.
References · 3
- 2015Deep Residual Learning for Image Recognitioncited by 52,096
- 2015Distilling the Knowledge in a Neural Networkcited by 10,324
- 2016FINN: A Framework for Fast, Scalable Binarized Neural Network Inferencecited by 150
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- 2023Design and Optimization of Residual Neural Network Accelerators for Low-Power FPGAs Using High-Level Synthesis ↗
- 2026DiffLUT-Net: Differentiable Training of FPGA LUT Networks with Learnable Connectivity
- 2025Energy-Efficient FPGA Framework for Non-Quantized Convolutional Neural Networks
- 2024Kratos: An FPGA Benchmark for Unrolled DNNs with Fine-Grained Sparsity and Mixed Precision
- 2024Efficiera Residual Networks: Hardware-Friendly Fully Binary Weight with 2-bit Activation Model Achieves Practical ImageNet Accuracy
- 2023ATHEENA: A Toolflow for Hardware Early-Exit Network Automation
- 2021Enabling Incremental Training with Forward Pass for Edge Devices
- 2023PERP: Rethinking the Prune-Retrain Paradigm in the Era of LLMs