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ConfuciuX: Autonomous Hardware Resource Assignment for DNN Accelerators using Reinforcement Learning

arXiv 2009.02010 ↗First posted 4 Sep 2020cs.AR cs.LG eess.SPcited by 35

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Abstract (arXiv)

DNN accelerators provide efficiency by leveraging reuse of activations/weights/outputs during the DNN computations to reduce data movement from DRAM to the chip. The reuse is captured by the accelerator's dataflow. While there has been significant prior work in exploring and comparing various dataflows, the strategy for assigning on-chip hardware resources (i.e., compute and memory) given a dataflow that can optimize for performance/energy while meeting platform constraints of area/power for DNN(s) of interest is still relatively unexplored. The design-space of choices for balancing compute and memory explodes combinatorially, as we show in this work (e.g., as large as O(10^(72)) choices for running mobilenet), making it infeasible to do manual-tuning via exhaustive searches. It is also difficult to come up with a specific heuristic given that different DNNs and layer types exhibit different amounts of reuse. In this paper, we propose an autonomous strategy called ConfuciuX to find optimized HW resource assignments for a given model and dataflow style. ConfuciuX leverages a reinforcement learning method, REINFORCE, to guide the search process, leveraging a detailed HW performance cost model within the training loop to estimate rewards. We also augment the RL approach with a genetic algorithm for further fine-tuning. ConfuciuX demonstrates the highest sample-efficiency for training compared to other techniques such as Bayesian optimization, genetic algorithm, simulated annealing, and other RL methods. It converges to the optimized hardware configuration 4.7 to 24 times faster than alternate techniques.

Key facts. Cited by 35 papers in the map (data through 7 Oct 2026). First posted on arXiv 4 Sep 2020.

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Citing papers per year: 2021: 12; 2022: 10; 2023: 4; 2024: 3; 2025: 4; 2026: 2.

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  1. 2023Full Stack Optimization of Transformer Inference: a Surveycited by 79
  2. 2021A Survey of Machine Learning for Computer Architecture and Systemscited by 53
  3. 2021AutoFL: Enabling Heterogeneity-Aware Energy Efficient Federated Learningcited by 39
  4. 2022Enable Deep Learning on Mobile Devices: Methods, Systems, and Applicationscited by 32
  5. 2021Data-Driven Offline Optimization For Architecting Hardware Acceleratorscited by 29
  6. 2021NAAS: Neural Accelerator Architecture Searchcited by 24
  7. 2021A Full-Stack Search Technique for Domain Optimized Deep Learning Acceleratorscited by 19
  8. 2021Pythia: A Customizable Hardware Prefetching Framework Using Online Reinforcement Learningcited by 17
  9. 2021MAGMA: An Optimization Framework for Mapping Multiple DNNs on Multiple Accelerator Corescited by 15
  10. 2024Functional Graphical Models: Structure Enables Offline Data-Driven Optimizationcited by 11
  11. 2021HASCO: Towards Agile HArdware and Software CO-design for Tensor Computationcited by 10
  12. 2022EF-Train: Enable Efficient On-device CNN Training on FPGA Through Data Reshaping for Online Adaptation or Personalizationcited by 8
23 more
  1. 2022DiGamma: Domain-aware Genetic Algorithm for HW-Mapping Co-optimization for DNN Acceleratorscited by 7
  2. 2022Special Session: Towards an Agile Design Methodology for Efficient, Reliable, and Secure ML Systemscited by 6
  3. 2023ArchGym: An Open-Source Gymnasium for Machine Learning Assisted Architecture Designcited by 6
  4. 2024SCAR: Scheduling Multi-Model AI Workloads on Heterogeneous Multi-Chiplet Module Acceleratorscited by 6
  5. 2021AIRCHITECT: Learning Custom Architecture Design and Mapping Spacecited by 4
  6. 2024Integrated Hardware Architecture and Device Placement Searchcited by 4
  7. 2025UbiMoE: A Ubiquitous Mixture-of-Experts Vision Transformer Accelerator With Hybrid Computation Pattern on FPGAcited by 4
  8. 2022DiVa: An Accelerator for Differentially Private Machine Learningcited by 3
  9. 2022FedGPO: Heterogeneity-Aware Global Parameter Optimization for Efficient Federated Learningcited by 3
  10. 2021RHNAS: Realizable Hardware and Neural Architecture Searchcited by 2
  11. 2022DNNFuser: Generative Pre-Trained Transformer as a Generalized Mapper for Layer Fusion in DNN Acceleratorscited by 2
  12. 2022Demystifying Map Space Exploration for NPUscited by 2
  13. 2021Self-Adaptive Reconfigurable Arrays (SARA): Using ML to Assist Scaling GEMM Accelerationcited by 1
  14. 2022GANDSE: Generative Adversarial Network based Design Space Exploration for Neural Network Accelerator Designcited by 1
  15. 2025AIRCHITECT v2: Learning the Hardware Accelerator Design Space through Unified Representationscited by 1
  16. 2025CORE: Constraint-Aware One-Step Reinforcement Learning for Simulation-Guided Neural Network Accelerator Designcited by 1
  17. 2026Athena: Synergizing Data Prefetching and Off-Chip Prediction via Online Reinforcement Learningcited by 1
  18. 2021Continual Learning Approach for Improving the Data and Computation Mapping in Near-Memory Processing Systemcited by 0
  19. 2022Multi-Agent Reinforcement Learning for Microprocessor Design Space Explorationcited by 0
  20. 2023Expediting Distributed DNN Training with Device Topology-Aware Graph Deploymentcited by 0
  21. 2023Statistical Hardware Design With Multi-model Active Learningcited by 0
  22. 2025SparseMap: A Sparse Tensor Accelerator Framework Based on Evolution Strategycited by 0
  23. 2026ChatNeuroSim: An LLM Agent Framework for Automated Compute-in-Memory Accelerator Deployment and Optimizationcited by 0