ConfuciuX: Autonomous Hardware Resource Assignment for DNN Accelerators using Reinforcement Learning
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Abstract (arXiv)
DNN accelerators provide efficiency by leveraging reuse of activations/weights/outputs during the DNN computations to reduce data movement from DRAM to the chip. The reuse is captured by the accelerator's dataflow. While there has been significant prior work in exploring and comparing various dataflows, the strategy for assigning on-chip hardware resources (i.e., compute and memory) given a dataflow that can optimize for performance/energy while meeting platform constraints of area/power for DNN(s) of interest is still relatively unexplored. The design-space of choices for balancing compute and memory explodes combinatorially, as we show in this work (e.g., as large as O(10^(72)) choices for running mobilenet), making it infeasible to do manual-tuning via exhaustive searches. It is also difficult to come up with a specific heuristic given that different DNNs and layer types exhibit different amounts of reuse. In this paper, we propose an autonomous strategy called ConfuciuX to find optimized HW resource assignments for a given model and dataflow style. ConfuciuX leverages a reinforcement learning method, REINFORCE, to guide the search process, leveraging a detailed HW performance cost model within the training loop to estimate rewards. We also augment the RL approach with a genetic algorithm for further fine-tuning. ConfuciuX demonstrates the highest sample-efficiency for training compared to other techniques such as Bayesian optimization, genetic algorithm, simulated annealing, and other RL methods. It converges to the optimized hardware configuration 4.7 to 24 times faster than alternate techniques.
Key facts. Cited by 35 papers in the map (data through 7 Oct 2026). First posted on arXiv 4 Sep 2020.
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Citing papers per year: 2021: 12; 2022: 10; 2023: 4; 2024: 3; 2025: 4; 2026: 2.
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- 2025UbiMoE: A Ubiquitous Mixture-of-Experts Vision Transformer Accelerator With Hybrid Computation Pattern on FPGA8 Feb 2025
- 2025AIRCHITECT v2: Learning the Hardware Accelerator Design Space through Unified Representations17 Jan 2025
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- 2022Enable Deep Learning on Mobile Devices: Methods, Systems, and Applications25 Apr 2022
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- 2022EF-Train: Enable Efficient On-device CNN Training on FPGA Through Data Reshaping for Online Adaptation or Personalization18 Feb 2022
- 2022DiGamma: Domain-aware Genetic Algorithm for HW-Mapping Co-optimization for DNN Accelerators26 Jan 2022
- 2022DNNFuser: Generative Pre-Trained Transformer as a Generalized Mapper for Layer Fusion in DNN Accelerators26 Jan 2022
- 2021Data-Driven Offline Optimization For Architecting Hardware Accelerators20 Oct 2021
- 2021Pythia: A Customizable Hardware Prefetching Framework Using Online Reinforcement Learning24 Sep 2021
- 2021AIRCHITECT: Learning Custom Architecture Design and Mapping Space16 Aug 2021
- 2021AutoFL: Enabling Heterogeneity-Aware Energy Efficient Federated Learning16 Jul 2021
- 2021RHNAS: Realizable Hardware and Neural Architecture Search17 Jun 2021
- 2021NAAS: Neural Accelerator Architecture Search27 May 2021
- 2021A Full-Stack Search Technique for Domain Optimized Deep Learning Accelerators26 May 2021
- 2021HASCO: Towards Agile HArdware and Software CO-design for Tensor Computation4 May 2021
- 2021MAGMA: An Optimization Framework for Mapping Multiple DNNs on Multiple Accelerator Cores28 Apr 2021
- 2021Continual Learning Approach for Improving the Data and Computation Mapping in Near-Memory Processing System28 Apr 2021
- 2021A Survey of Machine Learning for Computer Architecture and Systems16 Feb 2021
- 2021Self-Adaptive Reconfigurable Arrays (SARA): Using ML to Assist Scaling GEMM Acceleration12 Jan 2021
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- 2021A Survey of Machine Learning for Computer Architecture and Systemscited by 53
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- 2021MAGMA: An Optimization Framework for Mapping Multiple DNNs on Multiple Accelerator Corescited by 15
- 2024Functional Graphical Models: Structure Enables Offline Data-Driven Optimizationcited by 11
- 2021HASCO: Towards Agile HArdware and Software CO-design for Tensor Computationcited by 10
- 2022EF-Train: Enable Efficient On-device CNN Training on FPGA Through Data Reshaping for Online Adaptation or Personalizationcited by 8
12 most cited of 33 All 33 (JSON)
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- 2025CORE: Constraint-Aware One-Step Reinforcement Learning for Simulation-Guided Neural Network Accelerator Design4 Jun 2025
- 2025AIRCHITECT v2: Learning the Hardware Accelerator Design Space through Unified Representations17 Jan 2025
- 2024Integrated Hardware Architecture and Device Placement Search18 Jul 2024
- 2024SCAR: Scheduling Multi-Model AI Workloads on Heterogeneous Multi-Chiplet Module Accelerators1 May 2024
- 2024Functional Graphical Models: Structure Enables Offline Data-Driven Optimization8 Jan 2024
- 2023ArchGym: An Open-Source Gymnasium for Machine Learning Assisted Architecture Design15 Jun 2023
- 2023Statistical Hardware Design With Multi-model Active Learning14 Mar 2023
- 2023Full Stack Optimization of Transformer Inference: a Survey27 Feb 2023
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- 2022FedGPO: Heterogeneity-Aware Global Parameter Optimization for Efficient Federated Learning30 Nov 2022
12 newest of 33 All 33 (JSON)