Block-Wise Mixed-Precision Quantization: Enabling High Efficiency for Practical ReRAM-based DNN Accelerators
Not on the map. Why?
Abstract (arXiv)
Resistive random access memory (ReRAM)-based processing-in-memory (PIM) architectures have demonstrated great potential to accelerate Deep Neural Network (DNN) training/inference. However, the computational accuracy of analog PIM is compromised due to the non-idealities, such as the conductance variation of ReRAM cells. The impact of these non-idealities worsens as the number of concurrently activated wordlines and bitlines increases. To guarantee computational accuracy, only a limited number of wordlines and bitlines of the crossbar array can be turned on concurrently, significantly reducing the achievable parallelism of the architecture. While the constraints on parallelism limit the efficiency of the accelerators, they also provide a new opportunity for fine-grained mixed-precision quantization. To enable efficient DNN inference on practical ReRAM-based accelerators, we propose an algorithm-architecture co-design framework called underlineBlock-underlineWise mixed-precision underlineQuantization (BWQ). At the algorithm level, BWQ-A introduces a mixed-precision quantization scheme at the block level, which achieves a high weight and activation compression ratio with negligible accuracy degradation. We also present the hardware architecture design BWQ-H, which leverages the low-bit-width models achieved by BWQ-A to perform high-efficiency DNN inference on ReRAM devices. BWQ-H also adopts a novel precision-aware weight mapping method to increase the ReRAM crossbar's throughput. Our evaluation demonstrates the effectiveness of BWQ, which achieves a 6.08x speedup and a 17.47x energy saving on average compared to existing ReRAM-based architectures.
Key facts. Cited by 4 papers in the map (data through 7 Oct 2026). First posted on arXiv 17 Oct 2023.
Builds on
No reference list yet.
Built on by
Citing papers per year: 2025: 2; 2026: 2.
4 papers.
- 2025OASIS: Outlier-Aware LUT-Based GEMM with Dual-Side Quantization for LLM Inference Accelerationcited by 2
- 2025End-to-End Transformer Acceleration Through Processing-in-Memory Architecturescited by 1
- 2026Vortex: Bridging Extreme Compression and Efficient LLM Inferencecited by 0
- 2026AIR-LLM: Broadcasting AI Weights over Radio for Memory-Free Edge LLM Inference via RF Computingcited by 0
- 2026AIR-LLM: Broadcasting AI Weights over Radio for Memory-Free Edge LLM Inference via RF Computing30 Sep 2026
- 2026Vortex: Bridging Extreme Compression and Efficient LLM Inference10 Sep 2026
- 2025End-to-End Transformer Acceleration Through Processing-in-Memory Architectures21 Nov 2025
- 2025OASIS: Outlier-Aware LUT-Based GEMM with Dual-Side Quantization for LLM Inference Acceleration30 Jul 2025