mlsanityData to 14 Oct 2026

Design Rules for Extreme-Edge Scientific Computing on AI Engines

arXiv 2604.19106 ↗First posted 21 Apr 2026cs.AR cs.AI cs.LGcited by 0

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Abstract (arXiv)

Extreme-edge scientific applications use machine learning models to analyze sensor data and make real-time decisions. Their stringent latency and throughput requirements demand small batch sizes and require that model weights remain fully on-chip. Spatial dataflow implementations are common for extreme-edge applications. Spatial dataflow works well for small networks, but it fails to scale to larger models due to inherent resource scaling limitations. AI Engines on modern FPGA SoCs offer a promising alternative with high compute density and additional on-chip memory. However, the architecture, programming model, and performance-scaling behavior of AI Engines differ fundamentally from those of the programmable logic, making direct comparison non-trivial and the benefits of using AI Engines unclear. This work addresses how and when extreme-edge scientific neural networks should be implemented on AI Engines versus programmable logic. We provide systematic architectural characterization and micro-benchmarking and introduce a latency-adjusted resource equivalence (LARE) metric that identifies when AI Engine implementations outperform programmable logic designs. We further propose spatial and API-level dataflow optimizations tailored to low-latency scientific inference. Finally, we demonstrate the successful deployment of end-to-end neural networks on AI Engines that cannot fit on programmable logic when using the hlsml toolchain.

Key facts. No citing papers in the map yet (data through 14 Oct 2026). Builds on 19 of its 36 references that are in the map. First posted on arXiv 21 Apr 2026.

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19 of 36 references.

References · 19

  1. 2016FINN: A Framework for Fast, Scalable Binarized Neural Network Inferencecited by 150
  2. 2021MLPerf Tiny Benchmarkcited by 124
  3. 2021hls4ml: An Open-Source Codesign Workflow to Empower Scientific Low-Power Machine Learning Devicescited by 62
  4. 2021A reconfigurable neural network ASIC for detector front-end data compression at the HL-LHCcited by 20
  5. 2022FastML Science Benchmarks: Accelerating Real-Time Scientific Edge Machine Learningcited by 12
  6. 2023MaxEVA: Maximizing the Efficiency of Matrix Multiplication on Versal AI Enginecited by 7
  7. 2023Low latency optical-based mode tracking with machine learning deployed on FPGAs on a tokamakcited by 7
  8. 2023CHARM: Composing Heterogeneous Accelerators for Matrix Multiply on Versal ACAP Architecturecited by 6
  9. 2025AIE4ML: An End-to-End Framework for Compiling Neural Networks for the Next Generation of AMD AI Enginescited by 5
  10. 2024Low-latency machine learning FPGA accelerator for multi-qubit-state discriminationcited by 4
  11. 2023SPARTA: Spatial Acceleration for Efficient and Scalable Horizontal Diffusion Weather Stencil Computationcited by 3
  12. 2023AIM: Accelerating Arbitrary-precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAPcited by 3
7 more
  1. 2022Exploring the Versal AI engines for accelerating stencil-based atmospheric advection simulationcited by 2
  2. 2023Exploiting On-chip Heterogeneity of Versal Architecture for GNN Inference Accelerationcited by 2
  3. 2024Architectural Implications of Neural Network Inference for High Data-Rate, Low-Latency Scientific Applicationscited by 2
  4. 2024Reliable edge machine learning hardware for scientific applicationscited by 2
  5. 2024CAT: Customized Transformer Accelerator Framework on Versal ACAPcited by 2
  6. 2024Analysis of Hardware Synthesis Strategies for Machine Learning in Collider Trigger and Data Acquisitioncited by 2
  7. 2026Machine Learning on Heterogeneous, Edge, and Quantum Hardware for Particle Physics (ML-HEQUPP)cited by 2

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