mlsanityData to 14 Oct 2026

D-Legion: A Scalable Many-Core Architecture for Accelerating Matrix Multiplication in Quantized LLMs

arXiv 2602.06252 ↗First posted 5 Feb 2026cs.ARcited by 0

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Abstract (arXiv)

The performance gains obtained by large language models (LLMs) are closely linked to their substantial computational and memory requirements. Quantized LLMs offer significant advantages with extremely quantized models, motivating the development of specialized architectures to accelerate their workloads. This paper proposes D-Legion, a novel scalable many-core architecture, designed using many adaptive-precision systolic array cores, to accelerate matrix multiplication in quantized LLMs. The proposed architecture consists of a set of Legions where each Legion has a group of adaptive-precision systolic arrays. D-Legion supports multiple computation modes, including quantized sparse and dense matrix multiplications. The block structured sparsity is exploited within a fully-sparse, or partially-sparse windows. In addition, memory accesses of partial summations (psums) are spatially reduced through parallel accumulators. Furthermore, data reuse is maximized through optimized scheduling techniques by multicasting matrix tiles across the Legions. A comprehensive design space exploration is performed in terms of Legion/core granularity to determine the optimal Legion configuration. Moreover, D-Legion is evaluated on attention workloads from two BitNet models, delivering up to 8.2× lower latency, up to 3.8× higher memory savings, and up to 3× higher psum memory savings compared to state-of-the-art work. D-Legion, with eight Legions and 64 total cores, achieves a peak throughput of 135.68 TOPS at a frequency of 1 GHz. A scaled version of D-Legion, with 32 Legions, is compared to Google TPUv4i, achieving up to 2.5× lower total latency, up to 2.3× higher total throughput, and up to 2.7× higher total memory savings.

Key facts. No citing papers in the map yet (data through 14 Oct 2026). Builds on 14 of its 30 references that are in the map. First posted on arXiv 5 Feb 2026.

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References · 14

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  10. 20241-bit AI Infra: Part 1.1, Fast and Lossless BitNet b1.58 Inference on CPUscited by 12
  11. 2022Scale-out Systolic Arrayscited by 5
  12. 2024DiP: A Scalable, Energy-Efficient Systolic Array for Matrix Multiplication Accelerationcited by 5
2 more
  1. 2021Taxonomy and Benchmarking of Precision-Scalable MAC Arrays Under Enhanced DNN Dataflow Representationcited by 1
  2. 2025ADiP: Adaptive-Precision Systolic Array for Matrix Multiplication Accelerationcited by 1

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