Integrating NVIDIA Deep Learning Accelerator (NVDLA) with RISC-V SoC on FireSim
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Abstract (arXiv)
NVDLA is an open-source deep neural network (DNN) accelerator which has received a lot of attention by the community since its introduction by Nvidia. It is a full-featured hardware IP and can serve as a good reference for conducting research and development of SoCs with integrated accelerators. However, an expensive FPGA board is required to do experiments with this IP in a real SoC. Moreover, since NVDLA is clocked at a lower frequency on an FPGA, it would be hard to do accurate performance analysis with such a setup. To overcome these limitations, we integrate NVDLA into a real RISC-V SoC on the Amazon cloud FPGA using FireSim, a cycle-exact FPGA-accelerated simulator. We then evaluate the performance of NVDLA by running YOLOv3 object-detection algorithm. Our results show that NVDLA can sustain 7.5 fps when running YOLOv3. We further analyze the performance by showing that sharing the last-level cache with NVDLA can result in up to 1.56x speedup. We then identify that sharing the memory system with the accelerator can result in unpredictable execution time for the real-time tasks running on this platform. We believe this is an important issue that must be addressed in order for on-chip DNN accelerators to be incorporated in real-time embedded systems.
Key facts. Cited by 4 papers in the map (data through 14 Oct 2026). First posted on arXiv 5 Mar 2019.
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Citing papers per year: 2025: 3; 2026: 1.
4 papers.
- 2025Accelerating LLM Inference with Flexible N:M Sparsity via A Fully Digital Compute-in-Memory Acceleratorcited by 3
- 2025NVR: Vector Runahead on NPUs for Sparse Memory Accesscited by 0
- 2025Hardware-Aware Data and Instruction Mapping for AI Tasks: Balancing Parallelism, I/O and Memory Tradeoffscited by 0
- 2026Is INT8 Portable? A Cross-Platform Measurement Study of Quantized Inference on Embedded and Automotive Acceleratorscited by 0
- 2026Is INT8 Portable? A Cross-Platform Measurement Study of Quantized Inference on Embedded and Automotive Accelerators14 Sep 2026
- 2025Hardware-Aware Data and Instruction Mapping for AI Tasks: Balancing Parallelism, I/O and Memory Tradeoffs4 Sep 2025
- 2025Accelerating LLM Inference with Flexible N:M Sparsity via A Fully Digital Compute-in-Memory Accelerator19 Apr 2025
- 2025NVR: Vector Runahead on NPUs for Sparse Memory Access19 Feb 2025