That Chip Has Sailed: A Critique of Unfounded Skepticism Around AI for Chip Design
Not on the map. Why?
Abstract (arXiv)
In 2020, we introduced a deep reinforcement learning method capable of generating superhuman chip layouts, which we then published in Nature and open-sourced on GitHub. AlphaChip has inspired an explosion of work on AI for chip design, and has been deployed in state-of-the-art chips across Alphabet and extended by external chipmakers. Even so, a non-peer-reviewed invited paper at ISPD 2023 questioned its performance claims, despite failing to run our method as described in Nature. For example, it did not pre-train the RL method (removing its ability to learn from prior experience), used substantially fewer compute resources (20x fewer RL experience collectors and half as many GPUs), did not train to convergence (standard practice in machine learning), and evaluated on test cases that are not representative of modern chips. Recently, Igor Markov published a meta-analysis of three papers: our peer-reviewed Nature paper, the non-peer-reviewed ISPD paper, and Markov's own unpublished paper (though he does not disclose that he co-authored it). Although AlphaChip has already achieved widespread adoption and impact, we publish this response to ensure that no one is wrongly discouraged from innovating in this impactful area.
Key facts. Cited by 5 papers in the map (data through 7 Oct 2026). Builds on 10 of its 37 references that are in the map. First posted on arXiv 15 Nov 2024.
Builds on
10 of 37 references.
References · 10
- 2020Chip Placement with Deep Reinforcement Learningcited by 83
- 2021On Joint Learning for Solving Placement and Routing in Chip Designcited by 44
- 2022MaskPlace: Fast Chip Placement via Reinforced Visual Representation Learningcited by 43
- 2023ChiPFormer: Transferable Chip Placement via Offline Decision Transformercited by 42
- 2023Macro Placement by Wire-Mask-Guided Black-Box Optimizationcited by 23
- 2019The Cost of Application-Class Processing: Energy and Performance Analysis of a Linux-ready 1.7GHz 64bit RISC-V Core in 22nm FDSOI Technologycited by 16
- 2023An Updated Assessment of Reinforcement Learning for Macro Placementcited by 11
- 2024Retrieval-Guided Reinforcement Learning for Boolean Circuit Minimizationcited by 10
- 2021Delving into Macro Placement with Reinforcement Learningcited by 8
- 2023The False Dawn: Reevaluating Google's Reinforcement Learning for Chip Macro Placementcited by 2
Built on by
Citing papers per year: 2025: 2; 2026: 3.
5 papers.
- 2025BBOPlace-Bench: Benchmarking Black-Box Optimization for Chip Placementcited by 4
- 2025TextBO: Bayesian Optimization in Language Space for Eval-Efficient Self-Improving AIcited by 3
- 2026FlowPlace: Flow Matching for Chip Placementcited by 0
- 2026How Can Reinforcement Learning Achieve Expert-level Placement?cited by 0
- 2026CARVE: Breaking Data Barriers in Chip Placement by Harnessing Reusable Expertisecited by 0
- 2026CARVE: Breaking Data Barriers in Chip Placement by Harnessing Reusable Expertise27 Sep 2026
- 2026How Can Reinforcement Learning Achieve Expert-level Placement?28 Apr 2026
- 2026FlowPlace: Flow Matching for Chip Placement26 Apr 2026
- 2025TextBO: Bayesian Optimization in Language Space for Eval-Efficient Self-Improving AI15 Nov 2025
- 2025BBOPlace-Bench: Benchmarking Black-Box Optimization for Chip Placement27 Oct 2025