An Updated Assessment of Reinforcement Learning for Macro Placement
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Abstract (arXiv)
We provide an improved assessment of Google Brain's deep reinforcement learning approach to macro placement and its updated Circuit Training (CT) implementation in GitHub. A stronger simulated annealing (SA) baseline leverages the "go-with-the-winners" metaheuristic and a multi-threading implementation. We develop and release new public benchmarks in sub-10nm technology: LEF/DEF for Google's 7nm TSMC Ariane protobuf and scaled variants, as well as testcases implemented in the open-source ASAP7 7nm research enablement. We evaluate from-scratch training and fine-tuning results for the latest "AlphaChip" release of Circuit Training, alongside multiple alternative macro placers. We also study the recently-published pre-training guidance in. A commercial place-and-route tool is used to provide "true reward" post-route power, performance and area metrics. All data, evaluation flows and related scripts are publicly available in the MacroPlacement GitHub repository. Our study affords insights into reproducibility and reporting in the research literature, and points out still-missing confirmations (e.g., of CT's scalability and pre-training methodology) that remain open questions for the research community.
Key facts. Cited by 11 papers in the map (data through 7 Oct 2026). Builds on 2 of its 68 references that are in the map. First posted on arXiv 21 Feb 2023.
Builds on
2 of 68 references.
References · 2
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Citing papers per year: 2023: 2; 2024: 4; 2025: 2; 2026: 3.
11 papers.
- 2025ORFS-agent: Tool-Using Agents for Chip Design Optimizationcited by 13
- 2024Benchmarking End-To-End Performance of AI-Based Chip Placement Algorithmscited by 12
- 2024Chip Placement with Diffusion Modelscited by 5
- 2024That Chip Has Sailed: A Critique of Unfounded Skepticism Around AI for Chip Designcited by 5
- 2023INVICTUS: Optimizing Boolean Logic Circuit Synthesis via Synergistic Learning and Searchcited by 3
- 2023The False Dawn: Reevaluating Google's Reinforcement Learning for Chip Macro Placementcited by 2
- 2024GOALPlace: Begin with the End in Mindcited by 1
- 2026MAGE: Human-Like Macro Placement via Agentic Multimodal Reasoningcited by 1
- 2025DALI-PD: Diffusion-based Synthetic Layout Heatmap Generation for ML in Physical Designcited by 0
- 2026Graph Computation Meets Circuit Algebra: A Task-Aligned Analysis of Graph Neural Networks for Electronic Design Automationcited by 0
- 2026CARVE: Breaking Data Barriers in Chip Placement by Harnessing Reusable Expertisecited by 0
- 2026CARVE: Breaking Data Barriers in Chip Placement by Harnessing Reusable Expertise27 Sep 2026
- 2026MAGE: Human-Like Macro Placement via Agentic Multimodal Reasoning20 Jul 2026
- 2026Graph Computation Meets Circuit Algebra: A Task-Aligned Analysis of Graph Neural Networks for Electronic Design Automation8 May 2026
- 2025DALI-PD: Diffusion-based Synthetic Layout Heatmap Generation for ML in Physical Design13 Jul 2025
- 2025ORFS-agent: Tool-Using Agents for Chip Design Optimization10 Jun 2025
- 2024That Chip Has Sailed: A Critique of Unfounded Skepticism Around AI for Chip Design15 Nov 2024
- 2024Chip Placement with Diffusion Models17 Jul 2024
- 2024GOALPlace: Begin with the End in Mind5 Jul 2024
- 2024Benchmarking End-To-End Performance of AI-Based Chip Placement Algorithms3 Jul 2024
- 2023The False Dawn: Reevaluating Google's Reinforcement Learning for Chip Macro Placement16 Jun 2023
- 2023INVICTUS: Optimizing Boolean Logic Circuit Synthesis via Synergistic Learning and Search22 May 2023