mlsanityData to 7 Oct 2026

PANTHER: A Programmable Architecture for Neural Network Training Harnessing Energy-efficient ReRAM

arXiv 1912.11516 ↗First posted 24 Dec 2019cs.DC cs.AR cs.ETcited by 16

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Abstract (arXiv)

The wide adoption of deep neural networks has been accompanied by ever-increasing energy and performance demands due to the expensive nature of training them. Numerous special-purpose architectures have been proposed to accelerate training: both digital and hybrid digital-analog using resistive RAM (ReRAM) crossbars. ReRAM-based accelerators have demonstrated the effectiveness of ReRAM crossbars at performing matrix-vector multiplication operations that are prevalent in training. However, they still suffer from inefficiency due to the use of serial reads and writes for performing the weight gradient and update step. A few works have demonstrated the possibility of performing outer products in crossbars, which can be used to realize the weight gradient and update step without the use of serial reads and writes. However, these works have been limited to low precision operations which are not sufficient for typical training workloads. Moreover, they have been confined to a limited set of training algorithms for fully-connected layers only. To address these limitations, we propose a bit-slicing technique for enhancing the precision of ReRAM-based outer products, which is substantially different from bit-slicing for matrix-vector multiplication only. We incorporate this technique into a crossbar architecture with three variants catered to different training algorithms. To evaluate our design on different types of layers in neural networks (fully-connected, convolutional, etc.) and training algorithms, we develop PANTHER, an ISA-programmable training accelerator with compiler support. Our evaluation shows that PANTHER achieves up to 8.02×, 54.21×, and 103× energy reductions as well as 7.16×, 4.02×, and 16× execution time reductions compared to digital accelerators, ReRAM-based accelerators, and GPUs, respectively.

Key facts. Cited by 16 papers in the map (data through 7 Oct 2026). First posted on arXiv 24 Dec 2019.

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Citing papers per year: 2022: 3; 2023: 3; 2024: 4; 2025: 4; 2026: 2.

16 papers.

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  1. 2023X-Former: In-Memory Acceleration of Transformerscited by 25
  2. 2023Towards Efficient In-memory Computing Hardware for Quantized Neural Networks: State-of-the-art, Open Challenges and Perspectivescited by 5
  3. 2024LLS: Local Learning Rule for Deep Neural Networks Inspired by Neural Activity Synchronizationcited by 5
  4. 2022An Experimental Evaluation of Machine Learning Training on a Real Processing-in-Memory Systemcited by 2
  5. 2024FARe: Fault-Aware GNN Training on ReRAM-based PIM Acceleratorscited by 2
  6. 2025Atleus: Accelerating Transformers on the Edge Enabled by 3D Heterogeneous Manycore Architecturescited by 2
  7. 2025LANCE: Low Rank Activation Compression for Efficient On-Device Continual Learningcited by 2
  8. 2022Thermal Heating in ReRAM Crossbar Arrays: Challenges and Solutionscited by 1
  9. 2023TransPimLib: A Library for Efficient Transcendental Functions on Processing-in-Memory Systemscited by 1
  10. 2025Current Opinions on Memristor-Accelerated Machine Learning Hardwarecited by 1
  11. 2022NEON: Enabling Efficient Support for Nonlinear Operations in Resistive RAM-based Neural Network Acceleratorscited by 0
  12. 2024Pruning for Improved ADC Efficiency in Crossbar-based Analog In-memory Acceleratorscited by 0
4 more
  1. 2024A Collaborative PIM Computing Optimization Framework for Multi-Tenant DNNcited by 0
  2. 2025M2RU: Memristive Minion Recurrent Unit for On-Chip Continual Learning at the Edgecited by 0
  3. 2026ThRIve: Thermally Robust CNN Inference via Low-Rank Adaptation in Heterogeneous PIM Architecturescited by 0
  4. 2026Making Analog Training Scale: Co-Designing Mapping, Optimizer, and Converterscited by 0