Tailor: Altering Skip Connections for Resource-Efficient Inference
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Abstract (arXiv)
Deep neural networks use skip connections to improve training convergence. However, these skip connections are costly in hardware, requiring extra buffers and increasing on- and off-chip memory utilization and bandwidth requirements. In this paper, we show that skip connections can be optimized for hardware when tackled with a hardware-software codesign approach. We argue that while a network's skip connections are needed for the network to learn, they can later be removed or shortened to provide a more hardware efficient implementation with minimal to no accuracy loss. We introduce Tailor, a codesign tool whose hardware-aware training algorithm gradually removes or shortens a fully trained network's skip connections to lower their hardware cost. Tailor improves resource utilization by up to 34% for BRAMs, 13% for FFs, and 16% for LUTs for on-chip, dataflow-style architectures. Tailor increases performance by 30% and reduces memory bandwidth by 45% for a 2D processing element array architecture.
Key facts. Cited by 6 papers in the map (data through 7 Oct 2026). Builds on 30 of its 54 references that are in the map. First posted on arXiv 18 Jan 2023.
Builds on
30 of 54 references.
References · 30
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18 more
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Built on by
Citing papers per year: 2024: 5; 2025: 0; 2026: 1.
6 papers.
- 2024A Lightweight Spatiotemporal Network for Online Eye Tracking with Event Cameracited by 14
- 2024Towards Narrowing the Generalization Gap in Deep Boolean Networkscited by 3
- 2026SwiftChannel: Algorithm-Hardware Co-Design for Deep Learning-Based 5G Channel Estimationcited by 1
- 2024AdaResNet: Enhancing Residual Networks with Dynamic Weight Adjustment for Improved Feature Integrationcited by 0
- 2024Error Diffusion: Post Training Quantization with Block-Scaled Number Formats for Neural Networkscited by 0
- 2024UNet--: Memory-Efficient and Feature-Enhanced Network Architecture based on U-Net with Reduced Skip-Connectionscited by 0
- 2026SwiftChannel: Algorithm-Hardware Co-Design for Deep Learning-Based 5G Channel Estimation3 May 2026
- 2024UNet--: Memory-Efficient and Feature-Enhanced Network Architecture based on U-Net with Reduced Skip-Connections24 Dec 2024
- 2024Error Diffusion: Post Training Quantization with Block-Scaled Number Formats for Neural Networks15 Oct 2024
- 2024Towards Narrowing the Generalization Gap in Deep Boolean Networks6 Sep 2024
- 2024AdaResNet: Enhancing Residual Networks with Dynamic Weight Adjustment for Improved Feature Integration19 Aug 2024
- 2024A Lightweight Spatiotemporal Network for Online Eye Tracking with Event Camera13 Apr 2024