Synapse Compression for Event-Based Convolutional-Neural-Network Accelerators
Not on the map. Why?
Abstract (arXiv)
Manufacturing-viable neuromorphic chips require novel computer architectures to achieve the massively parallel and efficient information processing the brain supports so effortlessly. Emerging event-based architectures are making this dream a reality. However, the large memory requirements for synaptic connectivity are a showstopper for the execution of modern convolutional neural networks (CNNs) on massively parallel, event-based (spiking) architectures. This work overcomes this roadblock by contributing a lightweight hardware scheme to compress the synaptic memory requirements by several thousand times, enabling the execution of complex CNNs on a single chip of small form factor. A silicon implementation in a 12-nm technology shows that the technique increases the system's implementation cost by only 2%, despite achieving a total memory-footprint reduction of up to 374x compared to the best previously published technique.
Key facts. Cited by 1 paper in the map (data through 7 Oct 2026). Builds on 16 of its 29 references that are in the map. First posted on arXiv 13 Dec 2021.
Builds on
16 of 29 references.
References · 16
- 2015Deep Residual Learning for Image Recognitioncited by 51,809
- 2015U-Net: Convolutional Networks for Biomedical Image Segmentationcited by 19,604
- 2017MobileNets: Efficient Convolutional Neural Networks for Mobile Vision Applicationscited by 3,827
- 2018YOLOv3: An Incremental Improvementcited by 2,652
- 2016Aggregated Residual Transformations for Deep Neural Networkscited by 2,540
- 2015Deep Compression: Compressing Deep Neural Networks with Pruning, Trained Quantization and Huffman Codingcited by 2,291
- 2017Quantization and Training of Neural Networks for Efficient Integer-Arithmetic-Only Inferencecited by 1,548
- 2016End to End Learning for Self-Driving Carscited by 1,000
- 2016XNOR-Net: ImageNet Classification Using Binary Convolutional Neural Networkscited by 829
- 2017Channel Pruning for Accelerating Very Deep Neural Networkscited by 697
- 2016EIE: Efficient Inference Engine on Compressed Deep Neural Networkcited by 291
- 2021Dive into Deep Learningcited by 111
4 more
- 2017A scalable multi-core architecture with heterogeneous memory structures for Dynamic Neuromorphic Asynchronous Processors (DYNAPs)cited by 51
- 2017NullHop: A Flexible Convolutional Neural Network Accelerator Based on Sparse Representations of Feature Mapscited by 39
- 2016Sigma Delta Quantized Networkscited by 13
- 2019AdaptivFloat: A Floating-point based Data Type for Resilient Deep Learning Inferencecited by 5
Built on by
Citing papers per year: 2025: 1.
1 paper.