Tensor Processing Primitives: A Programming Abstraction for Efficiency and Portability in Deep Learning & HPC Workloads
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Abstract (arXiv)
During the past decade, novel Deep Learning (DL) algorithms, workloads and hardware have been developed to tackle a wide range of problems. Despite the advances in workload and hardware ecosystems, the programming methodology of DL systems is stagnant. DL workloads leverage either highly-optimized, yet platform-specific and inflexible kernels from DL libraries, or in the case of novel operators, reference implementations are built via DL framework primitives with underwhelming performance. This work introduces the Tensor Processing Primitives (TPP), a programming abstraction striving for efficient, portable implementation of DL workloads with high-productivity. TPPs define a compact, yet versatile set of 2D-tensor operators (or a virtual Tensor ISA), which subsequently can be utilized as building-blocks to construct complex operators on high-dimensional tensors. The TPP specification is platform-agnostic, thus code expressed via TPPs is portable, whereas the TPP implementation is highly-optimized and platform-specific. We demonstrate the efficacy and viability of our approach using standalone kernels and end-to-end DL & HPC workloads expressed entirely via TPPs that outperform state-of-the-art implementations on multiple platforms.
Key facts. Cited by 8 papers in the map (data through 7 Oct 2026). Builds on 26 of its 71 references that are in the map. First posted on arXiv 12 Apr 2021.
Builds on
26 of 71 references.
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Citing papers per year: 2022: 1; 2023: 2; 2024: 2; 2025: 2; 2026: 1.
8 papers.
- 2025ML-SpecQD: Multi-Level Speculative Decoding with Quantized Draftscited by 9
- 2023oneDNN Graph Compiler: A Hybrid Approach for High-Performance Deep Learning Compilationcited by 7
- 2024Generative Active Learning for the Search of Small-molecule Protein Binderscited by 6
- 2023Harnessing Deep Learning and HPC Kernels via High-Level Loop and Tensor Abstractions on CPU Architecturescited by 4
- 2024Towards a high-performance AI compiler with upstream MLIRcited by 3
- 2025Pushing the Envelope of LLM Inference with Ultra-Low-Bit Quantized Modelscited by 1
- 2022DistGNN-MB: Distributed Large-Scale Graph Neural Network Training on x86 via Minibatch Samplingcited by 0
- 2026Space Filling Curves is All You Need: Communication-Avoiding Matrix Multiplication Made Simplecited by 0
- 2026Space Filling Curves is All You Need: Communication-Avoiding Matrix Multiplication Made Simple22 Jan 2026
- 2025Pushing the Envelope of LLM Inference with Ultra-Low-Bit Quantized Models8 Aug 2025
- 2025ML-SpecQD: Multi-Level Speculative Decoding with Quantized Drafts17 Mar 2025
- 2024Generative Active Learning for the Search of Small-molecule Protein Binders2 May 2024
- 2024Towards a high-performance AI compiler with upstream MLIR15 Apr 2024
- 2023Harnessing Deep Learning and HPC Kernels via High-Level Loop and Tensor Abstractions on CPU Architectures25 Apr 2023
- 2023oneDNN Graph Compiler: A Hybrid Approach for High-Performance Deep Learning Compilation3 Jan 2023
- 2022DistGNN-MB: Distributed Large-Scale Graph Neural Network Training on x86 via Minibatch Sampling11 Nov 2022