Stripe: Tensor Compilation via the Nested Polyhedral Model
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Abstract (arXiv)
Hardware architectures and machine learning (ML) libraries evolve rapidly. Traditional compilers often fail to generate high-performance code across the spectrum of new hardware offerings. To mitigate, engineers develop hand-tuned kernels for each ML library update and hardware upgrade. Unfortunately, this approach requires excessive engineering effort to scale or maintain with any degree of state-of-the-art performance. Here we present a Nested Polyhedral Model for representing highly parallelizable computations with limited dependencies between iterations. This model provides an underlying framework for an intermediate representation (IR) called Stripe, amenable to standard compiler techniques while naturally modeling key aspects of modern ML computing. Stripe represents parallelism, efficient memory layout, and multiple compute units at a level of abstraction amenable to automatic optimization. We describe how Stripe enables a compiler for ML in the style of LLVM that allows independent development of algorithms, optimizations, and hardware accelerators. We also discuss the design exploration advantages of Stripe over kernel libraries and schedule-based or schedule-space-based code generation.
Key facts. Cited by 6 papers in the map (data through 14 Oct 2026). First posted on arXiv 14 Mar 2019.
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Citing papers per year: 2021: 3; 2022: 1; 2023: 2.
6 papers.
- 2022TensorIR: An Abstraction for Automatic Tensorized Program Optimizationcited by 38
- 2021The CoRa Tensor Compiler: Compilation for Ragged Tensors with Minimal Paddingcited by 17
- 2021Tensor Processing Primitives: A Programming Abstraction for Efficiency and Portability in Deep Learning & HPC Workloadscited by 9
- 2021Neural Architecture Search as Program Transformation Explorationcited by 8
- 2023oneDNN Graph Compiler: A Hybrid Approach for High-Performance Deep Learning Compilationcited by 7
- 2023Harnessing Deep Learning and HPC Kernels via High-Level Loop and Tensor Abstractions on CPU Architecturescited by 5
- 2023Harnessing Deep Learning and HPC Kernels via High-Level Loop and Tensor Abstractions on CPU Architectures25 Apr 2023
- 2023oneDNN Graph Compiler: A Hybrid Approach for High-Performance Deep Learning Compilation3 Jan 2023
- 2022TensorIR: An Abstraction for Automatic Tensorized Program Optimization9 Jul 2022
- 2021The CoRa Tensor Compiler: Compilation for Ragged Tensors with Minimal Padding19 Oct 2021
- 2021Tensor Processing Primitives: A Programming Abstraction for Efficiency and Portability in Deep Learning & HPC Workloads12 Apr 2021
- 2021Neural Architecture Search as Program Transformation Exploration12 Feb 2021