Rule2DRC: Benchmarking LLM Agents for DRC Script Synthesis with Execution-Guided Test Generation
On the map: LLM agents and tool use → Software engineering coding agents
Abstract (arXiv)
Manufacturable chip layouts must satisfy thousands of geometry-based design rules, and design rule checking (DRC) enforces them by running executable DRC scripts on layouts. Translating natural language rules into correct DRC scripts is labor-intensive and requires specialized expertise, motivating LLM agents for DRC script synthesis and debugging. However, existing benchmarks have small evaluation sets and often evaluate scripts by code similarity rather than execution correctness, and prior machine learning-based methods either ignore execution feedback or require labeled test layouts as agent's input. To this end, we introduce Rule2DRC, a large-scale benchmark for DRC script coding agents with 1,000 rule-to-script tasks and 13,921 evaluation chip layouts for execution-based scoring. Rule2DRC provides an evaluation pipeline that measures functional correctness via DRC execution outcomes without requiring evaluation layouts as input to the agent. We also propose SplitTester, a tester agent for program selection that uses execution feedback to generate discriminative test cases and separate previously indistinguishable candidate scripts, substantially improving Best-of-N selection performance in this domain. We release the code at https://github.com/snu-mllab/Rule2DRC.
Key facts. Cited by 3 papers in the map (data through 14 Oct 2026). Placed in Software engineering coding agents, one of 16 directions in LLM agents and tool use. Builds on 13 of its 26 references that are in the map. First posted on arXiv 15 May 2026.
Builds on
13 of 26 references.
References · 13
- 2023Judging LLM-as-a-Judge with MT-Bench and Chatbot Arenacited by 8,626
- 2021Evaluating Large Language Models Trained on Codecited by 8,320
- 2023Efficient Memory Management for Large Language Model Serving with PagedAttentioncited by 5,944
- 2023Let's Verify Step by Stepcited by 3,789
- 2024Large Language Monkeys: Scaling Inference Compute with Repeated Samplingcited by 991
- 2023Teaching Large Language Models to Self-Debugcited by 988
- 2024Code Generation with AlphaCodium: From Prompt Engineering to Flow Engineeringcited by 103
- 2025S*: Test Time Scaling for Code Generationcited by 98
- 2025Co-Evolving LLM Coder and Unit Tester via Reinforcement Learningcited by 56
- 2025CodeMonkeys: Scaling Test-Time Compute for Software Engineeringcited by 51
- 2025Dynamic Scaling of Unit Tests for Code Reward Modelingcited by 33
- 2024DRC-Coder: Automated DRC Checker Code Generation Using LLM Autonomous Agentcited by 15
1 more
- 2025An AST-guided LLM Approach for SVRF Code Synthesiscited by 3
Built on by
Citing papers per year: 2026: 3.
3 papers.
- 2026SCALE: Self-Supervised Constraint-Aware Layout GEneration for Local P&R DRV Fixing at Advanced Nodescited by 0
- 2026EngIntervene: Benchmarking Multimodal Engineering State Understanding and Design Intervention Reasoningcited by 0
- 20262d-fet-bench: from spatial reasoning to fet design on flakescited by 0
- 20262d-fet-bench: from spatial reasoning to fet design on flakes5 Oct 2026
- 2026EngIntervene: Benchmarking Multimodal Engineering State Understanding and Design Intervention Reasoning27 Sep 2026
- 2026SCALE: Self-Supervised Constraint-Aware Layout GEneration for Local P&R DRV Fixing at Advanced Nodes23 Jul 2026
Similar, not cited
Close in wording, no citation either way
- 2026DRC-Aid: Design-Rule Correction via Agentic Framework utilizing Inference-Time Large Language Models
- 2026ProcCtrlBench: Evaluating Process-Level Defects and Control Preservation in LLM Coding Agents
- 2026DRCY: Agentic Hardware Design Reviews
- 2025CodeARC: Benchmarking Reasoning Capabilities of LLM Agents for Inductive Program Synthesis
- 2025VFlow: Discovering Optimal Agentic Workflows for Verilog Generation
- 2025VeriMind: Agentic LLM for Automated Verilog Generation with a Novel Evaluation Metric
- 2026Bridging the Last Mile of Circuit Design: PostEDA-Bench, a Hierarchical Benchmark for PPA Convergence and DRC Fixing
- 2025Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verification