mlsanityData to 14 Oct 2026

MOCAP: Wafer-Scale-Chip-Oriented Memory-Orchestrated Chunked Pipelining Framework for Prefill-Only LLM Inference

arXiv 2606.22968 ↗First posted 22 Jun 2026cs.ARcited by 0

On the map: Efficient LLM inference and serving → Serving systems and request scheduling

Abstract (arXiv)

Large language models (LLMs) are increasingly used in prefill-only workloads, where end-to-end latency is dominated by the prefill phase. For long-context prefill, communication overhead grows with sequence length and quickly becomes a bottleneck on conventional GPU systems, making wafer-scale chips (WSCs) a promising substrate due to their high communication bandwidth and large aggregate compute and memory capacity. A natural way to accelerate prefill is to partition a long input sequence into multiple chunks and execute them in a finer-grained pipeline across devices. However, directly applying this idea to long-context prefill on WSCs remains challenging. First, causal dependency across chunks causes KV cache to accumulate unevenly across pipeline stages, creating severe memory imbalance and limiting the feasible sequence length. Second, later chunks require more attention computation because each chunk depends on preceding chunks, leading to chunk-level latency imbalance. To address these challenges, we present MOCAP, a memory-orchestrated chunked pipelining framework for prefill-only LLM inference on WSCs. MOCAP introduces Memory-Balanced KV Reallocation (MBKR) to alleviate memory imbalance by redistributing KV cache across pipeline stages, thereby extending the feasible sequence length. It further incorporates Latency-Balanced Chunk Partitioning (LBCP) to balance chunk execution cost under both attention-cost growth and KV reallocation overhead, improving pipeline efficiency. Experimental results show that, compared with GPipe, MOCAP achieves 76.4% lower end-to-end latency and 3.24× higher throughput on average. MOCAP also extends the maximum supported sequence length by up to 1.31× compared with Terapipe.

Key facts. No citing papers in the map yet (data through 14 Oct 2026). Placed in Serving systems and request scheduling, one of 12 directions in Efficient LLM inference and serving. Builds on 18 of its 41 references that are in the map. First posted on arXiv 22 Jun 2026.

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18 of 41 references.

Closest ancestors · 2

Same direction, newest first

  1. 2025MCBP: A Memory-Compute Efficient LLM Inference Accelerator Leveraging Bit-Slice-enabled Sparsity and Repetitiveness12 Sep
  2. 2025WaferLLM: Large Language Model Inference at Wafer Scale6 Feb

Other references · 16

  1. 2024Actions Speak Louder than Words: Trillion-Parameter Sequential Transducers for Generative Recommendationscited by 188
  2. 2021TeraPipe: Token-Level Pipeline Parallelism for Training Large-Scale Language Modelscited by 75
  3. 2023ASTRA-sim2.0: Modeling Hierarchical Networks and Disaggregated Systems for Large-model Training at Scalecited by 47
  4. 2025PrefillOnly: An Inference Engine for Prefill-only Workloads in Large Language Model Applicationscited by 21
  5. 2024SOFA: A Compute-Memory Optimized Sparsity Accelerator via Cross-Stage Coordinated Tilingcited by 9
  6. 2023Wafer-scale Computing: Advancements, Challenges, and Future Perspectivescited by 6
  7. 2025MoEntwine: Unleashing the Potential of Wafer-scale Chips for Large-scale Expert Parallel Inferencecited by 3
  8. 2026Ouroboros: Wafer-Scale SRAM CIM with Token-Grained Pipelining for Large Language Model Inferencecited by 3
  9. 2025WATOS: Efficient LLM Training Strategies and Architecture Co-exploration for Wafer-scale Chipcited by 2
  10. 2025PADE: A Predictor-Free Sparse Attention Accelerator via Unified Execution and Stage Fusioncited by 2
  11. 2024PALM: A Efficient Performance Simulator for Tiled Accelerators with Large-scale Model Trainingcited by 1
  12. 2024FRED: Flexible REduction-Distribution Interconnect and Communication Implementation for Wafer-Scale Distributed Training of DNN Modelscited by 1
4 more
  1. 2025BitStopper: An Efficient Transformer Attention Accelerator via Stage-fusion and Early Terminationcited by 1
  2. 2025LAPA: Log-Domain Prediction-Driven Dynamic Sparsity Accelerator for Transformer Modelcited by 1
  3. 2025TEMP: A Memory Efficient Physical-aware Tensor Partition-Mapping Framework on Wafer-scale Chipscited by 1
  4. 2025Designing Spatial Architectures for Sparse Attention: STAR Accelerator via Cross-Stage Tilingcited by 1

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  1. 2026VPP: Virtual Pipeline Parallelism for Efficient Chunked Prefill in Long-Context LLM Inference
  2. 2025Understanding Bottlenecks for Efficiently Serving LLM Inference With KV Offloading
  3. 2025Architecting Long-Context LLM Acceleration with Packing-Prefetch Scheduler and Ultra-Large Capacity On-Chip Memories
  4. 2025Accelerating LLM Inference Throughput via Asynchronous KV Cache Prefetching
  5. 2026KVDrive: A Holistic Multi-Tier KV Cache Management System for Long-Context LLM Inference
  6. 2023SARATHI: Efficient LLM Inference by Piggybacking Decodes with Chunked Prefills
  7. 2026ScoutAttention: Efficient KV Cache Offloading via Layer-Ahead CPU Pre-computation for LLM Inference
  8. 2024PipeInfer: Accelerating LLM Inference using Asynchronous Pipelined Speculation