SOFA: A Compute-Memory Optimized Sparsity Accelerator via Cross-Stage Coordinated Tiling
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Abstract (arXiv)
Benefiting from the self-attention mechanism, Transformer models have attained impressive contextual comprehension capabilities for lengthy texts. The requirements of high-throughput inference arise as the large language models (LLMs) become increasingly prevalent, which calls for large-scale token parallel processing (LTPP). However, existing dynamic sparse accelerators struggle to effectively handle LTPP, as they solely focus on separate stage optimization, and with most efforts confined to computational enhancements. By re-examining the end-to-end flow of dynamic sparse acceleration, we pinpoint an ever-overlooked opportunity that the LTPP can exploit the intrinsic coordination among stages to avoid excessive memory access and redundant computation. Motivated by our observation, we present SOFA, a cross-stage compute-memory efficient algorithm-hardware co-design, which is tailored to tackle the challenges posed by LTPP of Transformer inference effectively. We first propose a novel leading zero computing paradigm, which predicts attention sparsity by using log-based add-only operations to avoid the significant overhead of prediction. Then, a distributed sorting and a sorted updating FlashAttention mechanism are proposed with a cross-stage coordinated tiling principle, which enables fine-grained and lightweight coordination among stages, helping optimize memory access and latency. Further, we propose a SOFA accelerator to support these optimizations efficiently. Extensive experiments on 20 benchmarks show that SOFA achieves 9.5× speed up and 71.5× higher energy efficiency than Nvidia A100 GPU. Compared to 8 SOTA accelerators, SOFA achieves an average 15.8× energy efficiency, 10.3× area efficiency and 9.3× speed up, respectively.
Key facts. Cited by 8 papers in the map (data through 7 Oct 2026). First posted on arXiv 15 Jul 2024.
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Citing papers per year: 2024: 1; 2025: 5; 2026: 2.
8 papers.
- 2024Large Language Model Inference Acceleration: A Comprehensive Hardware Perspectivecited by 36
- 2025MCBP: A Memory-Compute Efficient LLM Inference Accelerator Leveraging Bit-Slice-enabled Sparsity and Repetitivenesscited by 4
- 2025Hardwired-Neurons Language Processing Units as General-Purpose Cognitive Substratescited by 1
- 2025BitStopper: An Efficient Transformer Attention Accelerator via Stage-fusion and Early Terminationcited by 1
- 2025LAPA: Log-Domain Prediction-Driven Dynamic Sparsity Accelerator for Transformer Modelcited by 1
- 2025CAMformer: Associative Memory is All You Needcited by 0
- 2026Salca: A Sparsity-Aware Hardware Accelerator for Efficient Long-Context Attention Decodingcited by 0
- 2026MOCAP: Wafer-Scale-Chip-Oriented Memory-Orchestrated Chunked Pipelining Framework for Prefill-Only LLM Inferencecited by 0
- 2026MOCAP: Wafer-Scale-Chip-Oriented Memory-Orchestrated Chunked Pipelining Framework for Prefill-Only LLM Inference22 Jun 2026
- 2026Salca: A Sparsity-Aware Hardware Accelerator for Efficient Long-Context Attention Decoding27 Apr 2026
- 2025BitStopper: An Efficient Transformer Attention Accelerator via Stage-fusion and Early Termination6 Dec 2025
- 2025LAPA: Log-Domain Prediction-Driven Dynamic Sparsity Accelerator for Transformer Model26 Nov 2025
- 2025CAMformer: Associative Memory is All You Need24 Nov 2025
- 2025MCBP: A Memory-Compute Efficient LLM Inference Accelerator Leveraging Bit-Slice-enabled Sparsity and Repetitiveness12 Sep 2025
- 2025Hardwired-Neurons Language Processing Units as General-Purpose Cognitive Substrates22 Aug 2025
- 2024Large Language Model Inference Acceleration: A Comprehensive Hardware Perspective6 Oct 2024