mlsanityData to 14 Oct 2026

ALADIN: Accuracy-Latency-Aware Design-space Inference Analysis for Embedded AI Accelerators

arXiv 2603.08722 ↗First posted 12 Feb 2026cs.AR cs.AI cs.LGcited by 0

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Abstract (arXiv)

The inference of deep neural networks (DNNs) on resource-constrained embedded systems introduces non-trivial trade-offs among model accuracy, computational latency, and hardware limitations, particularly when real-time constraints must be satisfied. This paper presents ALADIN, an accuracy-latency-aware design-space inference analysis framework for mixed-precision quantized neural networks (QNNs) targeting scratchpad-based AI accelerators. ALADIN enables the evaluation and analysis of inference bottlenecks and design trade-offs across accuracy, latency, and resource consumption without requiring deployment on the target platform, thereby significantly reducing development time and cost. The framework introduces a progressive refinement process that transforms a canonical QONNX model into platform-aware representations by integrating both platform-independent implementation details and hardware-specific characteristics. ALADIN is validated using a cycle-accurate simulator of a RISC-V based platform specialized for AI workloads, demonstrating its effectiveness as a tool for quantitative inference analysis and hardware-software co-design. Experimental results highlight how architectural decisions and mixed-precision quantization strategies impact accuracy, latency, and resource usage, and show that these effects can be precisely evaluated and compared using ALADIN, while also revealing subtle optimization tensions.

Key facts. No citing papers in the map yet (data through 14 Oct 2026). Builds on 25 of its 49 references that are in the map. First posted on arXiv 12 Feb 2026.

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References · 25

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  12. 2020Automatic heterogeneous quantization of deep neural networks for low-latency inference on the edge for particle detectorscited by 80
13 more
  1. 2022A Comprehensive Survey on Model Quantization for Deep Neural Networks in Image Classificationcited by 65
  2. 2020DORY: Automatic End-to-End Deployment of Real-World DNNs on Low-Cost IoT MCUscited by 58
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  4. 2017Parallel Multi Channel Convolution using General Matrix Multiplicationcited by 30
  5. 2023A Survey on Deep Learning Hardware Accelerators for Heterogeneous HPC Platformscited by 21
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  13. 2025QuantuneV2: Compiler-Based Local Metric-Driven Mixed Precision Quantization for Practical Embedded AI Applicationscited by 2

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  3. 2023SpaceEvo: Hardware-Friendly Search Space Design for Efficient INT8 Inference
  4. 2025Hardware-Aware Neural Network Compilation with Learned Optimization: A RISC-V Accelerator Approach
  5. 2024Exploring Quantization and Mapping Synergy in Hardware-Aware Deep Neural Network Accelerators
  6. 2025MaRVIn: A Cross-Layer Mixed-Precision RISC-V Framework for DNN Inference, from ISA Extension to Hardware Acceleration
  7. 2021HAO: Hardware-aware neural Architecture Optimization for Efficient Inference
  8. 2022Low- and Mixed-Precision Inference Accelerators