mlsanityData to 7 Oct 2026

Re2MaP: Macro Placement by Recursively Prototyping and Packing Tree-based Relocating

arXiv 2511.08054 ↗First posted 11 Nov 2025cs.AR cs.CV cs.SYcited by 0

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Abstract (arXiv)

This work introduces the Re2MaP method, which generates expert-quality macro placements through recursively prototyping and packing tree-based relocating. We first perform multi-level macro grouping and PPA-aware cell clustering to produce a unified connection matrix that captures both wirelength and dataflow among macros and clusters. Next, we use DREAMPlace to build a mixed-size placement prototype and obtain reference positions for each macro and cluster. Based on this prototype, we introduce ABPlace, an angle-based analytical method that optimizes macro positions on an ellipse to distribute macros uniformly near chip periphery, while optimizing wirelength and dataflow. A packing tree-based relocating procedure is then designed to jointly adjust the locations of macro groups and the macros within each group, by optimizing an expertise-inspired cost function that captures various design constraints through evolutionary search. Re2MaP repeats the above process: Only a subset of macro groups are positioned in each iteration, and the remaining macros are deferred to the next iteration to improve the prototype's accuracy. Using a well-established backend flow with sufficient timing optimizations, Re2MaP achieves up to 22.22% (average 10.26%) improvement in worst negative slack (WNS) and up to 97.91% (average 33.97%) improvement in total negative slack (TNS) compared to the state-of-the-art academic placer Hier-RTLMP. It also ranks higher on WNS, TNS, power, design rule check (DRC) violations, and runtime than the conference version ReMaP, across seven tested cases. Our code is available at https://github.com/lamda-bbo/Re2MaP.

Key facts. No citing papers in the map yet (data through 7 Oct 2026). Builds on 13 of its 48 references that are in the map. First posted on arXiv 11 Nov 2025.

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References · 13

  1. 2018A Tutorial on Bayesian Optimizationcited by 734
  2. 2021On Joint Learning for Solving Placement and Routing in Chip Designcited by 44
  3. 2022MaskPlace: Fast Chip Placement via Reinforced Visual Representation Learningcited by 43
  4. 2023ChiPFormer: Transferable Chip Placement via Offline Decision Transformercited by 42
  5. 2023Macro Placement by Wire-Mask-Guided Black-Box Optimizationcited by 23
  6. 2024Benchmarking End-To-End Performance of AI-Based Chip Placement Algorithmscited by 12
  7. 2023Hier-RTLMP: A Hierarchical Automatic Macro Placer for Large-scale Complex IP Blockscited by 11
  8. 2024Reinforcement Learning Policy as Macro Regulator Rather than Macro Placercited by 10
  9. 2025Evolution of Optimization Algorithms for Global Placement via Large Language Modelscited by 6
  10. 2024DG-RePlAce: A Dataflow-Driven GPU-Accelerated Analytical Global Placement Framework for Machine Learning Acceleratorscited by 4
  11. 2025Timing-Driven Global Placement by Efficient Critical Path Extractioncited by 4
  12. 2025Open3DBench: Open-Source Benchmark for 3D-IC Backend Implementation and PPA Evaluationcited by 4
1 more
  1. 2025Recursive Learning-Based Virtual Buffering for Analytical Global Placementcited by 1

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