NANQ: Noise-Floor-Aware Mixed-Precision Non-Uniform Quantization for Analog Compute-in-Memory
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Abstract (arXiv)
Analog compute-in-memory (CIM) enables energy-efficient neural network inference, but device variation and read noise can severely degrade low-bit quantized models. Existing CIM-oriented quantization methods mainly minimize ideal quantization error, ignoring the hardware noise floor and thus causing inefficient precision allocation. We propose NANQ, a noise-aware mixed-precision non-uniform quantization framework for analog CIM. NANQ models magnitude-dependent weight noise from measured responses of an eFlash CIM array and converts the noise profile into an adaptive quantization density, assigning finer resolution to low-noise regions while avoiding ineffective precision in noise-dominated regions. It further assigns layer-wise bit-widths by identifying each layer's precision saturation point under hardware noise using a unified threshold. On-chip experiments on an eFlash CIM SoC show that, under 2-bit weight-magnitude quantization, NANQ improves vision-model accuracy by 8.05 percentage points and reduces language-model PPL by 54.7% on average over PowerQuant. Mixed-precision NANQ captures most of the gains obtainable from additional quantization resources with only 3.2-3.8 equivalent bits.
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References · 5
- 2014ImageNet Large Scale Visual Recognition Challengecited by 8,498
- 2016Pointer Sentinel Mixture Modelscited by 3,096
- 2017Incremental Network Quantization: Towards Lossless CNNs with Low-Precision Weightscited by 217
- 2019Additive Powers-of-Two Quantization: An Efficient Non-uniform Discretization for Neural Networkscited by 148
- 2023PowerQuant: Automorphism Search for Non-Uniform Quantizationcited by 20
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- 2025Extending Straight-Through Estimation for Robust Neural Networks on Analog CIM Hardware
- 2026NOVA-CIM: Noise- and Correlation-Tolerant Stochastic Interfaces for Analog Compute-in-Memory
- 2023On-Chip Hardware-Aware Quantization for Mixed Precision Neural Networks
- 2025Rapid yet accurate Tile-circuit and device modeling for Analog In-Memory Computing
- 2025Analog Foundation Models
- 2021PR-CIM: a Variation-Aware Binary-Neural-Network Framework for Process-Resilient Computation-in-memory
- 2023Examining the Role and Limits of Batchnorm Optimization to Mitigate Diverse Hardware-noise in In-memory Computing
- 2026Selective KV Cache Protection for Noise-Resilient LLM Inference on Analog Compute-In-Memory Systems